Patents by Inventor Walter J. Ghijsen

Walter J. Ghijsen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10303828
    Abstract: A method for simulating an integrated circuit design is provided. The method includes executing a characterization tool over a first portion of a parameter space of a circuit design to form a netlist associated with the first portion of the parameter space. The method also includes forming a first sub-netlist from the netlist, selecting, for the first sub-netlist, a condition from at least one of a process, a voltage, or a temperature condition, and at least one parameter from the first portion of the parameter space. The method further includes executing a simulation of the first sub-netlist in a selected solver mode using the condition and the at least one parameter, and incorporating a result of the simulation in a circuit performance report, wherein the result is associated with the condition, with the at least one parameter, and with the first sub-netlist.
    Type: Grant
    Filed: May 5, 2017
    Date of Patent: May 28, 2019
    Assignee: CADENCE DESIGN SYSTEMS, INC.
    Inventors: Jaideep Mukherjee, Saibal Saha, Jianyu Li, Yishan Wang, Walter J. Ghijsen
  • Patent number: 10248745
    Abstract: A method for simulating an integrated circuit design is provided. The method includes forming a partition of an IC netlist into blocks based on a performance value from at least a portion of a parameter space and forming a table with parameter values including multiple instances of at least one block of the partition. The computer-implemented method also includes analyzing a direct-current (DC) solution of at least one block by combining at least a first instance of a first block with a second instance of a second block based on the performance value from the portion of the parameter space, and performing a transient analysis where signals change over time for the at least one block.
    Type: Grant
    Filed: May 5, 2017
    Date of Patent: April 2, 2019
    Assignee: CADENCE DESIGN SYSTEMS, INC.
    Inventors: Jaideep Mukherjee, Saibal Saha, Jianyu Li, Yishan Wang, Walter J. Ghijsen
  • Patent number: 10248747
    Abstract: A method for simulating an integrated circuit (IC) is provided. The method includes parsing an IC and loading the IC into memory and forming a table model including parameter values for at least one circuit component in the IC, the parameter values selected from a portion of a parameter space, storing a data value associated with the parsing of the IC and the table model in a database accessible through a cloud computing environment, the data value comprising a metadata associated with the data value, loading, to a processor, at least one of the data value or the metadata from the database, modifying the data value or the metadata that is loaded in the processor, according to the portion of the parameter space, and performing an analysis on at least one block of the IC according to the data value or the metadata that is loaded in the processor.
    Type: Grant
    Filed: May 5, 2017
    Date of Patent: April 2, 2019
    Assignee: CADENCE DESIGN SYSTEMS, INC.
    Inventors: Jaideep Mukherjee, Saibal Saha, Jianyu Li, Yishan Wang, Walter J. Ghijsen
  • Patent number: 8856700
    Abstract: In one embodiment of the invention, a method of synthesizing a circuit design is disclosed including receiving an input model of an initial circuit design into an electronic design automation system; receiving a user specification detailing a reliability feature to add to the initial circuit design; adding the reliability feature to the input model based upon the user specification to generate a modified input model; and producing an output model of a circuit design with the reliability feature in response to the modified input model.
    Type: Grant
    Filed: March 13, 2008
    Date of Patent: October 7, 2014
    Assignee: Cadence Design Systems, Inc.
    Inventors: Yosinori Watanabe, Walter J. Ghijsen, Michael J. Meyer, Michael T. Y. McNamara, David Van Campenhout
  • Patent number: 6381563
    Abstract: A system and method for generating inline subcircuits that enable a circuit designer to model and simulate circuits that when compared to conventional system and methods reduces the hierarchy from the perspective of the circuit designer, more efficiently models parasitic components, more efficiently parameterizes device models, more effectively creates models that are compatible with other simulation tools, can change the interface of a component without requiring the designer to use an extra layer of hierarchy, provides a more efficient interface by hiding details from the designer, enables hidden monitors and other functional designs to be automatically simulated by hiding these functions from the designer in a design level that is below the design level that is of interest to the designer, such as the geometrical parameter design level, can perform general purpose model binning with automatic selection, can export models and model parameters to other hierarchies without requiring an additional hierarchy in
    Type: Grant
    Filed: January 22, 1999
    Date of Patent: April 30, 2002
    Assignee: Cadence Design Systems, Inc.
    Inventors: Donald J. O'Riordan, Walter J. Ghijsen, Kenneth S. Kundert