Abstract: Processor methods and apparatus for adaptable network processing having speed advantages often associated with hardware implementations of network processing code or logic, as is often achieved using ASICs, for example, but at the same time having reconfigurability advantages often associated with software implementations of this code or logic. Methods and apparatus are described for adaptable hardware devices, such as a field programmable gate array (FPGA) or a circuit using FPGAs, to execute network processing code or logic. Methods and apparatus are described for using a software based device to program adaptable hardware devices to implement desired network processing code or logic.