Patents by Inventor Walter Katz

Walter Katz has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7937681
    Abstract: A method and system that converges on a global solution to a PCB routing problem using iterations of topology-based routing is described. In some embodiments, the geometric design space is abstracted into a topological graph representing the routing problem. Then, each net is allowed to find its optimal solution path independent of the solution paths for all other nets. The electrical and physical constraints of the system are initially ignored or greatly relaxed. Over each design iteration, the constraints are tightened until a complete, global, topological solution is found. Once a topological solution is found, it is converted into a geometric solution. In the event that no geometric solution exists for that topological solution, then the iteration process is resumed taking into consideration this additional information. The result is the ability to quickly autoroute highly-constrained PCB designs with minimal operator input.
    Type: Grant
    Filed: April 25, 2005
    Date of Patent: May 3, 2011
    Assignee: Cadence Design Systems, Inc.
    Inventors: Ken Wadland, Richard Allen Woodward, Jr., Randall Lawson, Walter Katz, Wiley Gillmor
  • Publication number: 20060242614
    Abstract: A method and system that converges on a global solution to a PCB routing problem using iterations of topology-based routing is described. In some embodiments, the geometric design space is abstracted into a topological graph representing the routing problem. Then, each net is allowed to find its optimal solution path independent of the solution paths for all other nets. The electrical and physical constraints of the system are initially ignored or greatly relaxed. Over each design iteration, the constraints are tightened until a complete, global, topological solution is found. Once a topological solution is found, it is converted into a geometric solution. In the event that no geometric solution exists for that topological solution, then the iteration process is resumed taking into consideration this additional information. The result is the ability to quickly autoroute highly-constrained PCB designs with minimal operator input.
    Type: Application
    Filed: April 25, 2005
    Publication date: October 26, 2006
    Applicant: Cadence Design Systems, Inc.
    Inventors: Ken Wadland, Richard Woodward, Randall Lawson, Walter Katz, Wiley Gillmor