Patents by Inventor Walter Neumueller

Walter Neumueller has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20110129299
    Abstract: A lining (2) for an inside surface of a tunnel, preferably the inside surface of tubbings, wherein it is provided in accordance with the invention that it comprises at least two layers of different tensile strength and extensibility.
    Type: Application
    Filed: November 18, 2010
    Publication date: June 2, 2011
    Applicant: agru Kunststofftechnik Gesellschaft m.b.H.
    Inventor: Walter Neumueller
  • Publication number: 20040053439
    Abstract: A method of fabricating a semiconductor connective region of a first conductivity type through a semiconductor layer of a second conductivity type which at least partly separates a bulk portion of semiconductor body (substrate) of the first conductivity type from a semiconductor well of the first conductivity type includes a step of implanting ions into a portion of the layer to convert the conductivity of the implanted portion to the first conductivity type. This electrically connects the well to the bulk portion of the body. Any biasing potential applied to the bulk portion of the body is thus applied to the well. This eliminates any need to form a contact in the well for biasing the well and thus allows the well to be reduced in size.
    Type: Application
    Filed: September 17, 2002
    Publication date: March 18, 2004
    Applicant: Infineon Technologies North America Corp.
    Inventors: Thomas Schafbauer, Klaus Schruefer, Odin Prigge, Reinhard Mahnkopf, Walter Neumueller
  • Patent number: 6136717
    Abstract: A method for producing a via hole to a doped region in a semiconductor device, including the steps of: producing the doped region in a substrate such that the doped region is limited by insulating regions at least at a surface of the substrate; depositing an undoped silicon layer surface-wide on the substrate; producing a doped region in the silicon layer that overlaps a region for the via hole; selectively removing the undoped silicon of the silicon layer relative to the doped region of the silicon layer; producing an insulating layer surface-wide; and forming the via hole in the insulating layer by selective anisotropic etching relative to the doped region of the silicon layer.
    Type: Grant
    Filed: April 27, 1993
    Date of Patent: October 24, 2000
    Assignee: Siemens Aktiengesellschaft
    Inventors: Josef Winnerl, Walter Neumueller