Patents by Inventor Walter P. Payack, Jr.

Walter P. Payack, Jr. has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20170180539
    Abstract: Electronic Locks used for physical access control will be able to wirelessly communicate directly with smartphone for selectable multi-factor authentication using technology and components built into Smartphones. Systems and methods utilize the phone's digital credential function, the phone's screen unlock keypad function, and the phone's biometric template information and comparison function to establish authentication parameters in order to unlock the door.
    Type: Application
    Filed: December 19, 2016
    Publication date: June 22, 2017
    Inventor: Walter P. PAYACK, JR.
  • Publication number: 20170098335
    Abstract: Electronic Locks used for physical access control will be able to wirelessly communicate directly with Smartphones for selectable multi-factor authentication using technology and components built into Smartphones. Systems and methods utilize the phone's digital credential function, the phone's screen unlock keypad function, and the phone's biometric template information and comparison function to establish authentication parameters in order to unlock the door.
    Type: Application
    Filed: October 3, 2016
    Publication date: April 6, 2017
    Inventor: Walter P. PAYACK, JR.
  • Patent number: 7085662
    Abstract: There is provided a method and a power quality indicator coupled to an electrical circuit. The indicator comprises the summing device configured to received a sensed wave form from the electrical circuit, including at least one voltage wave form. A summing device is configured to provide a summed output voltage. A low pass filter (LPF) is electrically coupled to the summing device and configured to receive a summed output voltage from the summing device. The LPF is configured to provide a LPF voltage. A microprocessor is configured to receive the sum upward voltage the LPF voltage, compute an RMS voltage value for each of the summed output voltage, determine the difference of such RMS voltage values and generate a signal representative of the difference of the RMS voltage values, wherein the signal is proportional to the harmonic content in the electrical circuit.
    Type: Grant
    Filed: July 30, 2004
    Date of Patent: August 1, 2006
    Assignee: Siemens Energy & Automation, Inc.
    Inventor: Walter P. Payack, Jr.