Patents by Inventor Walter Parmon
Walter Parmon has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11031681Abstract: A method of manufacturing a packaged semiconductor device is provided. The method includes attaching a semiconductor die to a package substrate. A bond pad of the semiconductor die is coupled to an antenna radiator formed on the package substrate. A waveguide is attached to the package substrate. An opening of the waveguide includes sidewalls substantially surrounding the antenna radiator. An epoxy material is deposited over at least a portion of the package substrate while leaving the opening void of epoxy material.Type: GrantFiled: June 20, 2019Date of Patent: June 8, 2021Assignee: NXP USA, INC.Inventors: Michael B. Vincent, Scott M. Hayes, Zhiwei Gong, Stephen Ryan Hooper, Pascal Oberndorff, Walter Parmon
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Publication number: 20200403298Abstract: A method of manufacturing a packaged semiconductor device is provided. The method includes attaching a semiconductor die to a package substrate. A bond pad of the semiconductor die is coupled to an antenna radiator formed on the package substrate. A waveguide is attached to the package substrate. An opening of the waveguide includes sidewalls substantially surrounding the antenna radiator. An epoxy material is deposited over at least a portion of the package substrate while leaving the opening void of epoxy material.Type: ApplicationFiled: June 20, 2019Publication date: December 24, 2020Inventors: Michael B. Vincent, Scott M. Hayes, Zhiwei Gong, Stephen Ryan Hooper, Pascal Oberndorff, Walter Parmon
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Patent number: 10651541Abstract: A method of manufacturing a packaged semiconductor device including forming an assembly by coupling a semiconductor die and an antenna by way of a substrate, contacting with a conformal structure at least a portion of a first surface of the antenna, and encapsulating the assembly with an encapsulant such that the at least a portion of the first surface of the antenna contacted by the conformal structure is not encapsulated with the encapsulant.Type: GrantFiled: February 27, 2019Date of Patent: May 12, 2020Assignee: NXP USA, INC.Inventors: Scott M. Hayes, Walter Parmon
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Patent number: 10615130Abstract: A packaged semiconductor device includes a substrate having a ground plane, a first communication port on the substrate, a second communication port on the substrate adjacent the first communication port, and grounding structures on the substrate. Each of the grounding structures is in contact with two different locations on the ground plane and is adjacent to one of the first and second communication ports. An electrically insulating material completely covers a top side of each of the grounding structures.Type: GrantFiled: November 29, 2018Date of Patent: April 7, 2020Assignee: NXP USA, Inc.Inventor: Walter Parmon
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Patent number: 10224255Abstract: Shielded and packaged electronic devices, electronic assemblies, and methods are disclosed herein. The shielded and packaged electronic devices include a packaged electronic device with a package surface and a plurality of electrically conductive package pads arranged on the package surface, a shielding dielectric layer extending in contact with the package surface and having a shielding layer surface and a plurality of openings that extends between the shielding layer surface and the plurality of electrically conductive package pads, and a plurality of electrical conductors that extends from the plurality of electrically conductive package pads and projects from the shielding layer surface. The electronic assemblies include a printed circuit board with a board surface and a plurality of electrically conductive board pads arranged on the board surface, the shielded and packaged electronic device, and an underfill dielectric layer. The methods include methods of manufacturing the electronic assemblies.Type: GrantFiled: June 14, 2016Date of Patent: March 5, 2019Assignee: NXP USA, Inc.Inventor: Walter Parmon
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Publication number: 20170359892Abstract: Shielded and packaged electronic devices, electronic assemblies, and methods are disclosed herein. The shielded and packaged electronic devices include a packaged electronic device with a package surface and a plurality of electrically conductive package pads arranged on the package surface, a shielding dielectric layer extending in contact with the package surface and having a shielding layer surface and a plurality of openings that extends between the shielding layer surface and the plurality of electrically conductive package pads, and a plurality of electrical conductors that extends from the plurality of electrically conductive package pads and projects from the shielding layer surface. The electronic assemblies include a printed circuit board with a board surface and a plurality of electrically conductive board pads arranged on the board surface, the shielded and packaged electronic device, and an underfill dielectric layer. The methods include methods of manufacturing the electronic assemblies.Type: ApplicationFiled: June 14, 2016Publication date: December 14, 2017Inventor: Walter Parmon
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Publication number: 20170092595Abstract: A method and apparatus are provided for manufacturing a packaged electronic device (200) which includes a carrier substrate (120) in which conductive interconnect paths (122) extend between first and second opposed surfaces, an integrated circuit die (125) affixed to the first surface of the carrier substrate for electrical connection to the plurality of conductive interconnect paths, and an array of conductors (110), such as BGA, LGA, PGA, C4 bump or flip chip conductors, affixed to the second surface of the carrier substrate for electrical connection to the plurality of conductive interconnect paths, where the array comprising a signal feed ball (112) and an array of shielding ground balls (111) surrounding the signal feed ball.Type: ApplicationFiled: September 29, 2015Publication date: March 30, 2017Applicant: FREESCALE SEMICONDUCTOR, INC.Inventor: Walter Parmon
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Patent number: 9589908Abstract: A method and apparatus are provided for manufacturing a packaged electronic device (200) which includes a carrier substrate (120) in which conductive interconnect paths (122) extend between first and second opposed surfaces, an integrated circuit die (125) affixed to the first surface of the carrier substrate for electrical connection to the plurality of conductive interconnect paths, and an array of conductors (110), such as BGA, LGA, PGA, C4 bump or flip chip conductors, affixed to the second surface of the carrier substrate for electrical connection to the plurality of conductive interconnect paths, where the array comprising a signal feed ball (112) and an array of shielding ground balls (111) surrounding the signal feed ball.Type: GrantFiled: September 29, 2015Date of Patent: March 7, 2017Assignee: NXP USA, INC.Inventor: Walter Parmon
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Patent number: 9553371Abstract: An integrated antenna package includes an interposer, an integrated circuit die, and a cap that forms a cavity within the integrated antenna package. A lossy EBG structure resides at the cap overlying the integrated circuit device. A lossless EBG structure resides at the cap overlying a microstrip feedline. A radar module includes a plurality of receive portions, each receive portion including a parabolic structure having a reflective surface, an absorber structure, a lens, and an antenna.Type: GrantFiled: November 12, 2010Date of Patent: January 24, 2017Assignee: NXP USA, INC.Inventors: James MacDonald, William McKinzie, III, Walter Parmon, Lawrence Rubin
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Patent number: 9386688Abstract: An integrated antenna package includes an interposer, an integrated circuit die, and a cap that forms a cavity within the integrated antenna package. A lossy ERG structure resides at the cap overlying the integrated circuit device. A lossless EBG structure resides at the cap overlying a microstrip feedline. A radar module includes a plurality of receive portions, each receive portion including a parabolic structure having a reflective surface, an absorber structure, a lens, and an antenna.Type: GrantFiled: November 12, 2010Date of Patent: July 5, 2016Assignee: Freescale Semiconductor, Inc.Inventors: James MacDonald, William McKinzie, III, Walter Parmon, Lawrence Rubin
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Patent number: 9190708Abstract: An electromagnetic band gap device is provided, comprising: a conductive plane; a non-conductive substrate located over the conductive plane; and an electromagnetic band gap unit cell that includes a first via located in the non-conductive substrate and filled with a conductive material, a second via located in the non-conductive substrate and filled with the conductive material, a first conductive surface located on the non-conductive substrate over the first via, and a second conductive surface located on the non-conductive substrate over the second via, wherein the electromagnetic band gap unit cell is configured to operate as an LC resonant circuit in conjunction with the conductive plane, at least one gap is located in the electromagnetic band gap unit cell, the at least one gap being located in the first via, in the first conductive surface, in the second conductive surface, and in the second via.Type: GrantFiled: March 5, 2013Date of Patent: November 17, 2015Assignee: Freescale Semiconductors, Inc.Inventor: Walter Parmon
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Publication number: 20140253258Abstract: An electromagnetic band gap device is provided, comprising: a conductive plane; a non-conductive substrate located over the conductive plane; and an electromagnetic band gap unit cell that includes a first via located in the non-conductive substrate and filled with a conductive material, a second via located in the non-conductive substrate and filled with the conductive material, a first conductive surface located on the non-conductive substrate over the first via, and a second conductive surface located on the non-conductive substrate over the second via, wherein the electromagnetic band gap unit cell is configured to operate as an LC resonant circuit in conjunction with the conductive plane, at least one gap is located in the electromagnetic band gap unit cell, the at least one gap being located in the first via, in the first conductive surface, in the second conductive surface, and in the second via.Type: ApplicationFiled: March 5, 2013Publication date: September 11, 2014Applicant: Freescale Semiconductor, Inc.Inventor: Walter PARMON
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Publication number: 20120119932Abstract: An integrated antenna package includes an interposer, an integrated circuit die, and a cap that forms a cavity within the integrated antenna package. A lossy EBG structure resides at the cap overlying the integrated circuit device. A lossless EBG structure resides at the cap overlying a microstrip feedline. A radar module includes a plurality of receive portions, each receive portion including a parabolic structure having a reflective surface, an absorber structure, a lens, and an antenna.Type: ApplicationFiled: November 12, 2010Publication date: May 17, 2012Applicant: FREESCALE SEMICONDUCTOR, INC.Inventors: James MacDonald, William McKinzie, III, Walter Parmon, Lawrence Rubin
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Publication number: 20120119969Abstract: An integrated antenna package includes an interposer, an integrated circuit die, and a cap that forms a cavity within the integrated antenna package. A lossy ERG structure resides at the cap overlying the integrated circuit device. A lossless EBG structure resides at the cap overlying a microstrip feedline. A radar module includes a plurality of receive portions, each receive portion including a parabolic structure having a reflective surface, an absorber structure, a lens, and an antenna.Type: ApplicationFiled: November 12, 2010Publication date: May 17, 2012Applicant: FREESCALE SEMICONDUCTOR, INC.Inventors: James MacDonald, William McKinzie, III, Walter Parmon, Lawrence Rubin
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Patent number: 7741718Abstract: Apparatus are provided for routing interconnects of a dual-gate electronic device operating in a differential configuration. An electronic apparatus formed on a substrate is provided comprising a first interconnect (40, 42, 44) configured to couple to a first region of the substrate, a first gate (22, 24, 26, 28) coupled to the first interconnect and configured to receive a first differential input, a second interconnect (30, 32, 34, 36, 38) parallel to the first interconnect and configured to couple to a second region of the substrate, and a second gate (20) coupled to the second interconnect and configured to receive a second differential input. The first gate is parallel to the first interconnect, and the second gate is parallel to the second interconnect.Type: GrantFiled: November 23, 2009Date of Patent: June 22, 2010Assignee: Freescale Semiconductor, Inc.Inventors: Suman K. Banerjee, Alain C. Duvalley, Olin L. Hartin, Craig Jasper, Walter Parmon
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Patent number: 7683486Abstract: Method and apparatus are provided for routing interconnects of a dual-gate electronic device operating in a differential configuration. An electronic apparatus formed on a substrate is provided comprising a first interconnect (40, 42, 44) configured to couple to a first region of the substrate, a first gate (22, 24, 26, 28) coupled to the first interconnect and configured to receive a first differential input, a second interconnect (30, 32, 34, 36, 38) parallel to the first interconnect and configured to couple to a second region of the substrate, and a second gate (20) coupled to the second interconnect and configured to receive a second differential input. The first gate is parallel to the first interconnect, and the second gate is parallel to the second interconnect.Type: GrantFiled: December 9, 2005Date of Patent: March 23, 2010Assignee: Freescale Semiconductor, Inc.Inventors: Suman K. Banerjee, Alain C. Duvallet, Craig Jasper, Olin L. Hartin, Walter Parmon
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Publication number: 20100065968Abstract: Apparatus are provided for routing interconnects of a dual-gate electronic device operating in a differential configuration. An electronic apparatus formed on a substrate is provided comprising a first interconnect (40, 42, 44) configured to couple to a first region of the substrate, a first gate (22, 24, 26, 28) coupled to the first interconnect and configured to receive a first differential input, a second interconnect (30, 32, 34, 36, 38) parallel to the first interconnect and configured to couple to a second region of the substrate, and a second gate (20) coupled to the second interconnect and configured to receive a second differential input. The first gate is parallel to the first interconnect, and the second gate is parallel to the second interconnect.Type: ApplicationFiled: November 23, 2009Publication date: March 18, 2010Applicant: FREESCALE SEMICONDUCTOR, INC.Inventors: Suman K. Banerjee, Alain C. Duvallet, Olin L. Hartin, Craig Jasper, Walter Parmon
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Publication number: 20070132062Abstract: Method and apparatus are provided for routing interconnects of a dual-gate electronic device operating in a differential configuration. An electronic apparatus formed on a substrate is provided comprising a first interconnect (40, 42, 44) configured to couple to a first region of the substrate, a first gate (22, 24, 26, 28) coupled to the first interconnect and configured to receive a first differential input, a second interconnect (30, 32, 34, 36, 38) parallel to the first interconnect and configured to couple to a second region of the substrate, and a second gate (20) coupled to the second interconnect and configured to receive a second differential input. The first gate is parallel to the first interconnect, and the second gate is parallel to the second interconnect.Type: ApplicationFiled: December 9, 2005Publication date: June 14, 2007Inventors: Suman Banerjee, Alain Duvallet, Olin Hartin, Craig Jasper, Walter Parmon