Abstract: Methods and apparatus for designing electronic circuits, including analog and mixed signal circuits. In one exemplary embodiment, a hierarchical design and sizing flow is used, in conjunction with one or more evaluation models (e.g., performance and feasibility models), such that results generated at one level remain valid and pertinent other levels of the hierarchy. In another aspect, hierarchical sizing is performed taking into consideration yield of the design via, e.g., a post-processing step which evaluates performance based on one or more existing performance models associated with the various levels of the hierarchy. A computer program embodying these methods, and a computer system adapted to run this program, are also disclosed.