Patents by Inventor Walter R. Buchanan
Walter R. Buchanan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20090297409Abstract: The present invention is generally directed to a single or dual dielectric barrier discharge reactor for generating flow discharge plasmas at atmospheric pressure or higher pressures. In particular, the present invention relates to a providing stable, energy efficient, glow discharge plasmas having a controlled discharge gap.Type: ApplicationFiled: May 30, 2008Publication date: December 3, 2009Inventors: Walter R. Buchanan, Christopher D. Hruska
-
Patent number: 6797992Abstract: The present invention provides a high voltage semiconductor device capable of withstanding excessive breakdown and clamping voltages. The device includes a high resistivity substrate, and an epitaxially grown, low resistivity layer having a stress-relieving dopant. During production, the low conductivity region has one surface that is etched before a high conductivity region is diffused into it or epitaxially deposited on it.Type: GrantFiled: August 7, 2001Date of Patent: September 28, 2004Assignee: FabTech, Inc.Inventors: Roman J. Hamerski, Walter R. Buchanan
-
Patent number: 6717229Abstract: A diode (20), having first and second conductive layers (24,26), a conductive pad (28), and a distributed reverse surge guard (22), provides increased protection from reverse current surges. The surge guard (22) includes an outer loop (42) of P+-type surge guard material and an inner grid (44) of linear sections (46, 48) which form a plurality of inner loops extending inside the outer loop (42). The surge guard (22) distributes any reverse current over the area of the conductive pad (28) to provide increased protection from transient threats such as electrostatic discharge (ESD) and during electrical testing.Type: GrantFiled: March 11, 2002Date of Patent: April 6, 2004Assignee: Fabtech, Inc.Inventors: Walter R. Buchanan, Roman J. Hamerski, Wayne A. Smith
-
Patent number: 6710419Abstract: An improved Schottky device, having a low resistivity layer of semiconductor material, a high resistivity layer of semiconductor material and a buried dopant region positioned in the high resistivity layer utilized to reduce reverse leakage current. The low resistivity layer can be an N+ material while the high resistivity layer can be an N− layer. The buried dopant region can be of P+ material, thus forming a PN junction with an associated charge depletion zone in the N− layer and an associated low reverse leakage current. The location of the P+ material allows for a full Schottky barrier between the N− material and a barrier metal to be maintained, thus the device experiences a low forward voltage drop.Type: GrantFiled: August 29, 2002Date of Patent: March 23, 2004Assignee: Fabtech, Inc.Inventors: Walter R. Buchanan, Roman J. Hamerski
-
Publication number: 20040046228Abstract: The present invention provides a high voltage semiconductor device capable of withstanding excessive breakdown and clamping voltages. The device includes a high resistivity substrate, and an epitaxially grown, low resistivity layer having a stress-relieving dopant. During production, the low conductivity region has one surface that is etched before a high conductivity region is diffused into it or epitaxially deposited on it.Type: ApplicationFiled: August 13, 2003Publication date: March 11, 2004Inventors: Roman J. Hamerski, Walter R. Buchanan
-
Publication number: 20030030069Abstract: The present invention provides a high voltage semiconductor device capable of withstanding excessive breakdown and clamping voltages. The device includes a high resistivity substrate, and an epitaxially grown, low resistivity layer having a stress-relieving dopant. During production, the low conductivity region has one surface that is etched before a high conductivity region is diffused into it or epitaxially deposited on it.Type: ApplicationFiled: August 7, 2001Publication date: February 13, 2003Inventors: Roman J. Hamerski, Walter R. Buchanan
-
Publication number: 20030006472Abstract: An improved Schottky device, having a low resistivity layer of semiconductor material, a high resistivity layer of semiconductor material and a buried dopant region positioned in the high resistivity layer utilized to reduce reverse leakage current. The low resistivity layer can be an N+ material while the high resistivity layer can be an N− layer. The buried dopant region can be of P+ material, thus forming a PN junction with an associated charge depletion zone in the N− layer and an associated low reverse leakage current. The location of the P+ material allows for a full Schottky barrier between the N− material and a barrier metal to be maintained, thus the device experiences a low forward voltage drop.Type: ApplicationFiled: August 29, 2002Publication date: January 9, 2003Inventors: Walter R. Buchanan, Roman J. Hamerski
-
Patent number: 6500741Abstract: An electrical device such as a diode usable in high voltage applications wherein the electrical device is fabricated from a method which yields a plurality of high voltage electrical devices, the present method including providing a substrate of a semiconductor material having a predetermined substrate conductive type, the substrate being typically formed from a monocrystalline growth method, forming a second epitaxial layer contiguous with the upper surface of the substrate, the epitaxial layer having a predetermined second layer conductive type, and thereafter forming a top layer of dopant material in a predetermined pattern upon the upper surface of the second epitaxial layer. This predetermined pattern of dopant material typically takes the form of an array of patches which can be achieved through either a masking and etching process, or through a screen printing process.Type: GrantFiled: March 28, 2002Date of Patent: December 31, 2002Assignee: Fabtech, Inc.Inventors: Walter R. Buchanan, Roman J. Hamerski
-
Patent number: 6479885Abstract: An electrical device such as a diode usable in high voltage applications wherein the electrical device is fabricated from a method which yields a plurality of high voltage electrical devices, the present method including providing a substrate of a semiconductor material having a predetermined substrate conductive type, the substrate being typically formed from a monocrystalline growth method, forming a second epitaxial layer contiguous with the upper surface of the substrate, the epitaxial layer having a predetermined second layer conductive type, and thereafter forming a top layer of dopant, material in a predetermined pattern upon the upper surface of the second epitaxial layer. This predetermined pattern of dopant material typically takes the form of an array of patches which can be achieved through either a masking and etching process, or through a screen printing process.Type: GrantFiled: March 28, 2002Date of Patent: November 12, 2002Assignee: Fabtech, Inc.Inventors: Walter R. Buchanan, Roman J. Hamerski
-
Patent number: 6462393Abstract: An improved Schottky device, having a low resistivity layer of semiconductor material, a high resistivity layer of semiconductor material and a buried dopant region positioned in the high resistivity layer utilized to reduce reverse leakage current. The low resistivity layer can be an N+ material while the high resistivity layer can be an N− layer. The buried dopant region can be of P+ material, thus forming a PN junction with an associated charge depletion zone in the N− layer and an associated low reverse leakage current. The location of the P+ material allows for a full Schottky barrier between the N− material and a barrier metal to be maintained, thus the device experiences a low forward voltage drop.Type: GrantFiled: March 20, 2001Date of Patent: October 8, 2002Assignee: FabTech, Inc.Inventors: Walter R. Buchanan, Roman J. Hamerski
-
Publication number: 20020135038Abstract: An improved Schottky device, having a low resistivity layer of semiconductor material, a high resistivity layer of semiconductor material and a buried dopant region positioned in the high resistivity layer utilized to reduce reverse leakage current. The low resistivity layer can be an N+ material while the high resistivity layer can be an N− layer. The buried dopant region can be of P+ material, thus forming a PN junction with an associated charge depletion zone in the N− layer and an associated low reverse leakage current. The location of the P+ material allows for a full Schottky barrier between the N− material and a barrier metal to be maintained, thus the device experiences a low forward voltage drop.Type: ApplicationFiled: March 20, 2001Publication date: September 26, 2002Inventors: Walter R. Buchanan, Roman J. Hamerski
-
Publication number: 20020105055Abstract: An electrical device such as a diode usable in high voltage applications wherein the electrical device is fabricated from a method which yields a plurality of high voltage electrical devices, the present method including providing a substrate of a semiconductor material having a predetermined substrate conductive type, the substrate being typically formed from a monocrystalline growth method, forming a second epitaxial layer contiguous with the upper surface of the substrate, the epitaxial layer having a predetermined second layer conductive type, and thereafter forming a top layer of dopant material in a predetermined pattern upon the upper surface of the second epitaxial layer. This predetermined pattern of dopant material typically takes the form of an array of patches which can be achieved through either a masking and etching process, or through a screen printing process.Type: ApplicationFiled: March 28, 2002Publication date: August 8, 2002Inventors: Walter R. Buchanan, Roman J. Hamerski
-
Publication number: 20020105044Abstract: A diode (20), having first and second conductive layers (24,26), a conductive pad (28), and a distributed reverse surge guard (22), provides increased protection from reverse current surges. The surge guard (22) includes an outer loop (42) of P+-type surge guard material and an inner grid (44) of linear sections (46, 48) which form a plurality of inner loops extending inside the outer loop (42). The surge guard (22) distributes any reverse current over the area of the conductive pad (28) to provide increased protection from transient threats such as electrostatic discharge (ESD) and during electrical testing.Type: ApplicationFiled: March 11, 2002Publication date: August 8, 2002Inventors: Walter R. Buchanan, Roman J. Hamerski, Wayne A. Smith
-
Publication number: 20020098632Abstract: An electrical device such as a diode usable in high voltage applications wherein the electrical device is fabricated from a method which yields a plurality of high voltage electrical devices, the present method including providing a substrate of a semiconductor material having a predetermined substrate conductive type, the substrate being typically formed from a monocrystalline growth method, forming a second epitaxial layer contiguous with the upper surface of the substrate, the epitaxial layer having a predetermined second layer conductive type, and thereafter forming a top layer of dopant material in a predetermined pattern upon the upper surface of the second epitaxial layer. This predetermined pattern of dopant material typically takes the form of an array of patches which can be achieved through either a masking and etching process, or through a screen printing process.Type: ApplicationFiled: March 28, 2002Publication date: July 25, 2002Inventors: Walter R. Buchanan, Roman J. Hamerski
-
Patent number: 6376346Abstract: An electrical device such as a diode usable in high voltage applications wherein the electrical device is fabricated from a method which yields a plurality of high voltage electrical devices, the present method including providing a substrate of a semiconductor material having a predetermined substrate conductive type, the substrate being typically formed from a monocrystalline growth method, forming a second epitaxial layer contiguous with the upper surface of the substrate, the epitaxial layer having a predetermined second layer conductive type, and thereafter forming a top layer of dopant material in a predetermined pattern upon the upper surface of the second epitaxial layer. This predetermined pattern of dopant material typically takes the form of an array of patches which can be achieved through either a masking and etching process, or through a screen printing process.Type: GrantFiled: September 28, 2000Date of Patent: April 23, 2002Assignee: FabTech, Inc.Inventors: Walter R. Buchanan, Roman J. Hamerski
-
Patent number: 5017508Abstract: A method and apparatus for annealing devices having radiation induced damage is disclosed. A device is exposed to electron irradiation to induce damage to the active area. The device is then annealed with a rapid thermal anneal at a low temperature. The rapid thermal anneal may, optionally, be followed by a conventional oven or furnace anneal at a temperature of about 300.degree. to 450.degree. C. The method produces devices having improved and well controlled characteristics such as short circuit operating area, power dissipated during switching, and on-state voltage drop.Type: GrantFiled: June 29, 1989Date of Patent: May 21, 1991Assignee: Ixys CorporationInventors: Darcy T. Dodt, Walter R. Buchanan