Abstract: The present invention is an electronic structure having a buffer layer with a short average carrier lifetime, at least about 1000 Å thick with an upper face, and an integrated circuit disposed over the upper face of the buffer layer, where this integrated circuit would otherwise be susceptible to soft errors, due to its configuration, its clock speed, its use environment, or a combination of these factors. In a preferred embodiment, the preferably high recombination rate buffer layer is an LT GaAs or GaAs:Er buffer layer.

Abstract: A semiconductor structure GaInAs provides significantly low output capacitance in a digital integrated circuit, such as an inverter. A dopant density (N) within the range of 1.0.times.10.sup.16 cm.sup.-3 and 4.7.times.10.sup.16 cm.sup.-3 and an active layer thickness (a) within the range of 0.15 micrometer and 0.33 micrometer are selected in proper combination to provide a design criterion to provide good device performance with a significantly small propagation delay between the input and output terminals.

Abstract: High power operation of an amplifier is more easily achieved in the 15 GHz and higher portion of the radio frequency spectrum by utilizing transmission line techniques to form the elements of the amplifier. Source, drain and gate members are arranged as elements of a radio frequency transmission line on a doped, semiconductor surface. When properly biased, the device operates as an amplifier.

Abstract: A transferred electron logic input device (TELD) is cascaded with a field effect transistor output device (FET) to provide a threshold gate having switching times compatible with gigabit rate logic and having the capability to drive low impedance loads.

Abstract: The interval between arrival of two time displaced signals is measured with a resolution less than 0.5 nanoseconds by electronic vernier techniques utilizing transferred electron logic device circuits. The first arriving signal triggers a first clock generator of pulse period T.sub.C, the pulses from which are counted by a first counter and a second counter. The second arriving signal triggers a second clock pulse generator having a pulse period T.sub.V, the first pulse therefrom disabling the first counter at a count of M. As T.sub.V <T.sub.C coincidence of the pulses from the two clock pulse generators will eventually occur causing disabling of the second counter at a count of N. Time interval .DELTA.T is computed from the formula: .DELTA.T=(N-1)T.sub.C -(N-M)T.sub.V.

Abstract: Two input signals, each being at either of two different amplitudes, are coupled to respective Schottky-barrier gates of one transferred electron logic device (TELD) of relatively low transit-time frequency and coupled via a delay means to respective Schottky-barrier gates of another TELD of relatively high transit-time frequency. When the two input signals are at different amplitudes, the TELD connected via the delay means becomes biased to domain formation, thereby causing an output signal having a first value to be produced. When both input signals are at one of the amplitudes, the other TELD becomes biased to domain formation, thereby causing an output signal having a second value to be produced. When both input signals are of the other of the amplitudes, neither TELD is biased to domain formation, thereby causing an output signal having a third value to be produced.

Abstract: A pulse train generator operating at subnanosecond periods includes a transferred-electron device (TED) in series with an open circuited resonant transmission line. The transmission line sustains domain formation in the TED. A filter coupled to the TED may be utilized to produce pulses at a subharmonic of the TED transit time frequency, determined by the length of the transmission line.

Abstract: A circuit is receptive of two time-spaced input signals at two respective input terminals, where either terminal may receive the first arriving input signal, for producing at first and second output terminals, signals indicative respectively of the time of arrival of the first and second input signals.