Abstract: Means for converting characters of a first 128-character alphabet (ASCII) into characters of a second 26-character alphabet are provided and convert each pair of characters of the first alphabet into three characters of the second alphabet and vice versa.The means are embodied by a suitably programmed computer. In the conversion, each pair of characters Z.sub.1, Z.sub.2 of the first alphabet are interpreted as numbers and divided by 26. The resulting largest multiples Q.sub.1, Q.sub.2 of 26 are multiplied by 1 and 5 respectively and the products are added. The remainders after division give the first two characters A.sub.1 and A.sub.2 out of each set of three characters of the second alphabet, and the sum of the products gives the third character A.sub.3. Reconversion is similar. First, Q.sub.2 is obtained by division as the largest integral multiple of 5 in A.sub.3 and Q.sub.1 is the remainder after division. Q.sub.1 and Q.sub.2 are then each multiplied by 26 and added to A.sub.1 and A.sub.

Abstract: An encipher-decipher apparatus including an input keyboard and a processing and control stage which enciphers or deciphers data received directly from the keyboard or preferably from a text store with the aid of a cipher generator. The cipher generator produces a cipher sequence dependent on two code data items that determine the initial state of the cipher generator. One item for encryption is supplied as a set of random code characters from a random generator. The random generator comprises a continually cycled modulo-n counter and a FIFO memory into which the instantaneous state of the counter is entered at each of successive actuations of keys of the keyboard, such key operations being those done in any event in the use of the apparatus. The cycle time of the counter is much less than the time between consecutive key operations. A clock rate of 100 kHz is suggested. The set of characters is read out of the FIFO store at the start of data processing for use by the cipher generator.

Abstract: A system for inserting extra-information bits into a bit sequence to be transmitted over a transmission channel and for suppressing such bits from the transmitted bit sequence, the system having an inserter at the transmitting end and a suppressor at the receiving end, the inserter converting an input bit sequence which it receives at a first repetition frequency into a second repetition frequency which is higher to correspond to the inserted extra bits, by the insertion of m extra bits per m.k.n bits of the input bit sequence k, n and m denoting integers which are greater than zero, the suppressor restoring the original input bit sequence at the first repetition frequency and the extra-information bits from the output bit sequence which it receives from the transmitter at the second repetition frequency, the inserter comprising a first repetition frequency generator which derives the output bit sequence repetition frequency from the input sequence repetition frequency and complies with the condition n.k.