Abstract: A circuit for determining the arrival times of control signals supplied to microprocessors is disclosed which eliminates the error caused by the interrupt delay. Additional counters are employed to eliminate the errors caused by the delay between the receipt of a control signal by a microprocessor and the corresponding output of a read command requesting the momentary reading of a first counter occurs. A second counter is used to eliminate the interrupt delay error by counting clock pulses from the arrival of the control signal until the read command is received. The counter reading from the second counter is subtracted from the first counter to determine the actual arrival time of the control signal.