Patents by Inventor Walter Stuart Venters

Walter Stuart Venters has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9807207
    Abstract: Methods, systems, and apparatus for preserving timing domains of different communications types of signals in a telecommunications network are disclosed. In one aspect a network element (NE) includes a receiver configured to receive communications signals of two different communications types. The NE can include a timing analyzer configured to obtain a local reference clock (LRC), detect two different received reference clocks (RRCs) corresponding to the two different communications types, and for each received communications signal, determine a quantized value (QV) based on a difference between the LRC and the RRC. The NE can include a timing generator configured to generate, for the received communications signal, a transmit reference clock (TRC) that is referenced to, but different from, each of the LRC and the QV. The NE can include a transmitter configured to output an output signal based on the received communications signal and the TRC for the received communications signal.
    Type: Grant
    Filed: March 26, 2015
    Date of Patent: October 31, 2017
    Assignee: ADTRAN, Inc.
    Inventors: Troy W. White, Walter Stuart Venters
  • Publication number: 20160285574
    Abstract: Methods, systems, and apparatus for preserving timing domains of different communications types of signals in a telecommunications network are disclosed. In one aspect a network element (NE) includes a receiver configured to receive communications signals of two different communications types. The NE can include a timing analyzer configured to obtain a local reference clock (LRC), detect two different received reference clocks (RRCs) corresponding to the two different communications types, and for each received communications signal, determine a quantized value (QV) based on a difference between the LRC and the RRC. The NE can include a timing generator configured to generate, for the received communications signal, a transmit reference clock (TRC) that is referenced to, but different from, each of the LRC and the QV. The NE can include a transmitter configured to output an output signal based on the received communications signal and the TRC for the received communications signal.
    Type: Application
    Filed: March 26, 2015
    Publication date: September 29, 2016
    Inventors: TROY W. WHITE, Walter Stuart Venters
  • Patent number: 7742505
    Abstract: An interworking function (IWF) is coupled to a switch of a packet network and communicates with the network switch based on an Ethernet clock signal or some other type of clock signal. A primary reference clock (PRC) of the network generates a PRC signal, and a timing analyzer determines timing information indicative of timing relationships between the Ethernet clock signal and the PRC signal. The timing analyzer periodically transmits such timing information, and the IWF uses the timing information to generate a PRC signal that is traceable to the network PRC signal.
    Type: Grant
    Filed: December 14, 2006
    Date of Patent: June 22, 2010
    Assignee: ADTRAN, Inc.
    Inventors: Walter Stuart Venters, Troy Wayne White, Daniel Patrick Day, Richard Goodson
  • Patent number: 6996071
    Abstract: A binary decision tree-based arbitration scheme executable by a control processor of a time division multiplex (TDM)-based communication system is operative to select the next packet to be transmitted from a plurality of virtual circuits, any number of which may have one or more packets awaiting transmission over a serialized digital communication link. The transmission priority scheme contains N+1 sets of nodes containing 2N+1?1 nodes. A respective ith set of nodes comprises 2i?1 nodes, wherein i is greater than or equal to 1, and less than or equal to N+1. The nodes of a given set are connected to those of an adjacent set by binary-split branches. For each of the 2N leaf nodes of the decision tree, information is stored representative of the transmission priority of a packet awaiting transmission from its associated communication port.
    Type: Grant
    Filed: April 30, 2001
    Date of Patent: February 7, 2006
    Assignee: Adtran Inc.
    Inventors: David Perkinson, Walter Stuart Venters
  • Publication number: 20020159397
    Abstract: A binary decision tree-based arbitration scheme executable by a control processor of a time division multiplex (TDM)-based communication system is operative to select the next packet to be transmitted from a plurality of virtual circuits, any number of which may have one or more packets awaiting transmission over a serialized digital communication link. The transmission priority scheme contains N+1 sets of nodes containing 2N+1−1 nodes. A respective ith set of nodes comprises 2i−1 nodes, wherein i is greater than or equal to 1, and less than or equal to N+1. The nodes of a given set are connected to those of an adjacent set by binary-split branches. For each of the 2N leaf nodes of the decision tree, information is stored representative of the transmission priority of a packet awaiting transmission from its associated communication port.
    Type: Application
    Filed: April 30, 2001
    Publication date: October 31, 2002
    Applicant: Adtran, Inc.
    Inventors: David Perkinson, Walter Stuart Venters