Abstract: A semiconductor substrate includes a high-resistivity silicon carbide layer and a gallium nitride epitaxial layer. The gallium nitride epitaxial layer is formed on a surface, a thickness of the gallium nitride epitaxial layer is less than 2 ?m, and a full width at half maximum (FWHM) of an X-ray diffraction analysis (002) plane is less than 100 arcsec. The thickness of the high-resistivity silicon carbide layer ranges from 20 ?m to 50 ?m. The surface of the high-resistivity silicon carbide layer has an angle ranging from 0° to +/?8° with respect to a (0001) plane. The micropipe density (MPD) of the high-resistivity silicon carbide layer is less than 0.5 ea/cm2, the basal plane dislocation (BPD) of the high-resistivity silicon carbide layer is less than 10 ea/cm2, and the threading screw dislocation (TSD) of the high-resistivity silicon carbide layer is less than 500 ea/cm2.

Abstract: A semiconductor substrate and a method of manufacturing the same are provided. The method includes epitaxially growing a buffer layer and a silicon carbide layer on a silicon surface of an N-type silicon carbide substrate, and the silicon carbide layer is high-resistivity silicon carbide or N-type silicon carbide (N—SiC). Next, a gallium nitride epitaxial layer is epitaxially grown on the silicon carbide layer to obtain a semiconductor structure composed of the buffer layer, the silicon carbide layer, and the gallium nitride epitaxial layer. After the epitaxial growth of the gallium nitride epitaxial layer, a laser is used to form a damaged layer in the semiconductor structure, and a chip carrier is bonded to the surface of the gallium nitride epitaxial layer, and then the N-type silicon carbide and the semiconductor structure are separated at the location of the damaged layer.

Abstract: A field effect transistor comprising: a first semiconductor structure, the first semiconductor structure having a channel layer; a second semiconductor structure, the second semiconductor structure is arranged on the first semiconductor structure, and the second semiconductor structure is stacked in sequence from bottom to top with a Schottky layer, a first etch stop layer, a wide recess layer, an ohmic contact layer, and a narrow recess, a wide recess is opened in the ohmic contact layer, so that the upper surface of the wide recess layer forms a wide recess area and the upper surface of the Schottky layer forms a narrow recess area; at least one delta-doped layer, a gate metal contact, the gate metal contact is formed inside the wide recess a source metal contact; and a drain metal contact, and the drain metal contact is located on the other side of the gate metal contact.

Abstract: A radio frequency integrated circuit comprising: at least one transistor; a matching circuit coupled to said transistor; and at least one bump is used to form a passive element in said matching circuit, and said bump is used for radio frequency matching, the bumps can be used as passive components for amplifier harmonic impedance matching or the bumps can be the amplifier's passive components of the harmonic impedance matching, both of them can enhance the power, bandwidth and efficiency of amplifiers and integrated circuits.

Abstract: A field effect transistor comprising: a first semiconductor structure, the first semiconductor structure having a channel layer; a second semiconductor structure, the second semiconductor structure is arranged on the first semiconductor structure, and the second semiconductor structure is stacked in sequence from bottom to top with a Schottky layer, a first etch stop layer, a wide recess layer, an ohmic contact layer, and a narrow recess, a wide recess is opened in the ohmic contact layer, so that the upper surface of the wide recess layer forms a wide recess area and the upper surface of the Schottky layer forms a narrow recess area; at least one delta-doped layer, a gate metal contact, the gate metal contact is formed inside the wide recess a source metal contact; and a drain metal contact, and the drain metal contact is located on the other side of the gate metal contact.

Abstract: A heterojunction bipolar transistor, comprising: a substrate, having a first surface and an opposite second surface; a sub-emitter layer arranged on the first surface; a compound emitter layer arranged on the sub-emitter layer, making the sub-emitter layer and the compound emitter layer forms an emitter layer; a base layer arranged on the compound emitter layer; a collector ledge layer arranged on the base layer; a collector layer arranged on the collector ledge layer; a lateral oxidation region arranged on the compound emitter layer forming a current blocking region, and the outer region of the compound emitter layer surrounds inner region, so that the inner region of the compound emitter layer forms a current aperture.

Abstract: A heterojunction bipolar transistor, comprising: a substrate, having a first surface and an opposite second surface; a sub-emitter layer arranged on the first surface; a compound emitter layer arranged on the sub-emitter layer, making the sub-emitter layer and the compound emitter layer forms an emitter layer; a base layer arranged on the compound emitter layer; a collector ledge layer arranged on the base layer; a collector layer arranged on the collector ledge layer; a lateral oxidation region arranged on the compound emitter layer forming a current blocking region, and the outer region of the compound emitter layer surrounds inner region, so that the inner region of the compound emitter layer forms a current aperture.

Abstract: A semiconductor substrate and a method of manufacturing the same are provided. The method includes epitaxially growing a buffer layer and a silicon carbide layer on a silicon surface of an N-type silicon carbide substrate, and the silicon carbide layer is high-resistivity silicon carbide or N-type silicon carbide (N—SiC). Next, a gallium nitride epitaxial layer is epitaxially grown on the silicon carbide layer to obtain a semiconductor structure composed of the buffer layer, the silicon carbide layer, and the gallium nitride epitaxial layer. After the epitaxial growth of the gallium nitride epitaxial layer, a laser is used to form a damaged layer in the semiconductor structure, and a chip carrier is bonded to the surface of the gallium nitride epitaxial layer, and then the N-type silicon carbide and the semiconductor structure are separated at the location of the damaged layer.

Abstract: A low stress moisture resistant structure of semiconductor device comprises a low stress moisture resistant layer, wherein a semiconductor device is formed on a semiconductor wafer, the semiconductor device comprises at least one pad, the low stress moisture resistant layer is coated on the semiconductor device and the semiconductor wafer so that a pad top center surface of the pad is exposed. The low stress moisture resistant layer comprises a material comprising crosslinked fluoropolymer. A before-coated stress measured on the semiconductor wafer before the low stress moisture resistant layer is coated and an after-cured stress measured on the semiconductor wafer after the low stress moisture resistant layer is coated and cured define a stress difference, the stress difference is greater than or equal to ?5×107 dyne/cm2 and less than or equal to 5×107 dyne/cm2.

Abstract: A GaN-based field effect transistor comprises a semiconductor substrate, an epitaxial structure formed on the semiconductor substrate, a source electrode, a drain electrode, and a gate electrode. The epitaxial structure comprises a buffer layer, a channel layer, a spacer layer, an n-type doped barrier layer, a barrier layer, and a capping layer, sequentially. The epitaxial structure has a source recess and a drain recess. A bottom of the source recess is defined by the n-type doped barrier layer or the spacer layer. A bottom of the drain recess is defined by the n-type doped barrier layer or the spacer layer. The source electrode is formed in the source recess. The drain electrode is formed in the drain recess. The gate electrode is formed on the capping layer between the source electrode and the drain electrode.

Abstract: A wideband impedance matching network comprises a fundamental output MN including a first portion and a second portion and a harmonic compensation MN including a harmonic MN portion and a harmonic MN backside-via inductor formed on an outer surface of a harmonic MN backside via hole penetrating through a semiconductor substrate. The first portion, the second portion and the harmonic MN portion are formed on the semiconductor substrate. A second terminal of the first portion and a first terminal of the second portion are connected to an RF output terminal. A first terminal of the harmonic MN portion and a first terminal of the first portion are connected to an RF input terminal. A second terminal of the harmonic MN portion is connected to a first terminal of the harmonic MN backside-via inductor. A second terminal of the harmonic MN backside-via inductor is grounded.

Abstract: A low stress moisture resistant structure of semiconductor device comprises a low stress moisture resistant layer, wherein a semiconductor device is formed on a semiconductor wafer, the semiconductor device comprises at least one pad, the low stress moisture resistant layer is coated on the semiconductor device and the semiconductor wafer so that a pad top center surface of the pad is exposed. The low stress moisture resistant layer comprises a material comprising crosslinked fluoropolymer. A before-coated stress measured on the semiconductor wafer before the low stress moisture resistant layer is coated and an after-cured stress measured on the semiconductor wafer after the low stress moisture resistant layer is coated and cured define a stress difference, the stress difference is greater than or equal to ?5×107 dyne/cm2 and less than or equal to 5×107 dyne/cm2.

Abstract: An improved high temperature resistant backside metallization for compound semiconductors comprises a front-side metal layer formed on a compound semiconductor substrate; at least one via hole penetrating the compound semiconductor substrate, a top of an inner surface of the via hole is defined by the front-side metal layer; at least one seed metal layer, at least one backside metal layer and at least one diffusion barrier layer sequentially formed on a bottom surface of the compound semiconductor substrate and the inner surface of the via hole, the seed metal layer and the front-side metal layer are electrically connected through the via hole; a die attachment metal layer formed on a bottom surface of the diffusion barrier layer other than the via hole and an adjacent area near the via hole. The diffusion barrier layer prevents the backside metal layer from diffusing into the die attachment metal layer.

Abstract: An improved passivation structure for GaN field effect transistor comprising at least one dielectric layer formed on a top surface of a GaN field effect transistor and a passivation layer formed on a top surface of the dielectric layer. The GaN field effect transistor has a gate electrode comprising a Schottky contact metal layer, at least one diffusion barrier metal layer and a high conductivity metal layer. The passivation layer is made of a low cure temperature Polybenzoxazole (PBO) which can be cured at a low-temperature. Thereby the intermixing of the Schottky contact metal layer and the the diffusion barrier metal layer are prevented.

Abstract: An improved high temperature resistant backside metallization for compound semiconductors comprises a front-side metal layer formed on a compound semiconductor substrate; at least one via hole penetrating the compound semiconductor substrate, a top of an inner surface of the via hole is defined by the front-side metal layer; at least one seed metal layer, at least one backside metal layer and at least one diffusion barrier layer sequentially formed on a bottom surface of the compound semiconductor substrate and the inner surface of the via hole, the seed metal layer and the front-side metal layer are electrically connected through the via hole; a die attachment metal layer formed on a bottom surface of the diffusion barrier layer other than the via hole and an adjacent area near the via hole. The diffusion barrier layer prevents the backside metal layer from diffusing into the die attachment metal layer.

Abstract: An improved gate metal structure for compound semiconductor devices comprises sequentially a compound semiconductor substrate, a Schottky barrier layer, an insulating layer and a gate metal. The insulating layer has a gate recess. The surrounding and the bottom of the gate recess are defined by the insulating layer and the Schottky barrier layer respectively. The gate metal includes a contact layer formed on the insulating layer, covering the gate recess and contacted with the Schottky barrier layer at the bottom of the gate recess; a first diffusion barrier layer formed on the contact layer; a second diffusion barrier layer formed on the first diffusion barrier layer; and a conduct layer formed on the second diffusion barrier layer. Thereby the reliability of the compound semiconductor devices is enhanced.

Abstract: A method to produce high electron mobility transistors with Boron implanted isolation comprises the following steps: on a substrate forming in sequence a nucleation layer, a buffer layer, a barrier layer and a cap layer; coating a photoresist layer on the cap layer; photomasking and by exposure eliminating the photoresist layer of at least one isolation region; executing plural times an ion implantation process including: adjusting an incident angle of a Boron ion beam with respect to the substrate, and implanting the Boron ion beam into the cap layer, the barrier layer, the buffer layer, the nucleation layer and the substrate within the at least one isolation region so as to form an isolation structure while rotating the substrate by a rotation angle; eliminating the rest of the photoresist layer by exposure; and forming a source, a drain and a gate on the cap layer.

Abstract: A wafer holding structure for wafer backside processing, in which the wafer comprises a SiC substrate and a semiconductor device layer. The SiC substrate has a back surface and a front surface, and the semiconductor device layer has a first surface and a second surface. The semiconductor device layer is disposed on the SiC substrate with its first surface in contact with the front surface of the SiC substrate. The wafer holding structure comprises a wafer carrier and an adhesive coating. The wafer carrier is made of n-type conductive SiC, and has a thermal expansion coefficient that is well matched to the SiC substrate. The wafer carrier is mounted to the second surface of the semiconductor device layer and the adhesive coating is coated between the wafer carrier and the second surface of the semiconductor device layer.

Abstract: A method for forming a through wafer via hole in a semiconductor device, wherein the semiconductor device comprises a wafer having a SiC substrate with a front side and a backside, a GaN-based layer formed on the front side of the SiC substrate, and a mask structure formed on the backside of the SiC substrate defining an etching area. The etching area is first descummed A through substrate via hole is formed by etching the etching area through the SiC substrate. The mask structure is removed and the inner surface of the through substrate via hole is cleaned. The inner surface of the through substrate via hole is then descummed A through wafer via hole is formed by etching through the GaN layer in the through substrate via hole. And lastly the inner surface of the through wafer via hole is cleaned.

Abstract: A wafer edge protector is used in an inductively coupled plasma reactive ion etching instrument for the manufacturing of GaN semiconductor devices and circuits. The wafer edge protector comprises a ring clamp, which has a first inner diameter and a second inner diameter, and the ring clamp covers the edges of a wafer and a wafer carrier to clamp the wafer and the wafer carrier and to prevent damage on the edges of the wafer and the wafer carrier during the etching process.