Abstract: In an arrangement for the bit-parallel addition of binary numbers in two's complement form, a series of adders (AD.sub.i) are provided to receive inputs for binary bits of equivalent significance and to emit intermediate sum and carry words which are combined to form result sum words. For the correction of overflow errors, the carry bit of the adder (AD.sub.n-2) having the second highest significance is replaced by the carry bit of the most significant adder (AD.sub.n-1) and, when the carry bits of the two most significant adders (AD.sub.n-1, AD.sub.n-2) are unequal, the intermediate sum bit of the most significant adder (AD.sub.n-1) is replaced by its carry bit.

Abstract: A carry-save adder for a bit-parallel addition of binary numbers in two's complement form incorporates a series of first adders for forming intermediate sum and carry words which are combined in an adder means to form a sum word. A decoder is provided for recognizing saturation of the carry-save adder and for generating overflow signals in dependence on the two most significant bits of the intermediate sum and carry words. When the overflow signals are generated, the recursive circuit branches are disconnected and saturation intermediate sum and carry words are substituted for the intermediate sum and carry words which yield sum words which do not exceed the permissible adder content.

Abstract: A method and apparatus for preparing samples of a time-dependent signal (Se) in a data processing system which comprises an arithmetic unity (1), a control unit (2), a memory (3) and an address modification unit (13) wherein with a stored dataset of individual samples, for updating these step-by-step during every successive sampling period and respectively reading out the dated dataset and supplying it to the arithmetic unit (1), is achieved such that an address sequence which traverses a prescribed memory area is output via the address modification unit (13), so that a sequence of samples is written. Subsequently, the memory area is cyclically traversed with a plurality of address strings, whereby the stored samples are successively read out onto a bus line (4) and, when reaching an individual memory location within each of the address strings, the oldest sample stored there is overwritten by a further sample. The method is distinguished by a minimum of re-storing operations.

Abstract: A digital arithmetic unit useful in data processing digital circuits comprises a plurality of stages each having two half-adders combined into a full adder and a carry logic element. An objective is to shorten the processing time for the addition and subtraction of binary numbers. For this purpose, the stages are divided into at least two groups and two separate carry paths are provided within each group. One of the carry paths is only switched on by means of selection logic elements. The activation occurs sequentially in group-wise fashion after simultaneous carry runs in all carry paths. The advantage particularly consists of the chronological coincidence of the carry runs in all groups.