Patents by Inventor Walter Wohlmuth

Walter Wohlmuth has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230282645
    Abstract: A semiconductor device includes an insulating layer, a semiconductor layer, and a compound semiconductor stacked layer disposed on a substrate in sequence, a first transistor, a second transistor, an isolation structure, and a conductive structure. The first transistor is disposed in a first device region and on the compound semiconductor stacked layer. The second transistor is disposed in a second device region and on the compound semiconductor stacked layer. The isolation structure is disposed between the first and second transistors. The conductive structure is disposed in the second device region, passes through the compound semiconductor stacked layer, and electrically connects the semiconductor layer to a second source of the second transistor. There is no electrical connection between the semiconductor layer in the first device region and a first source of the first transistor.
    Type: Application
    Filed: March 2, 2022
    Publication date: September 7, 2023
    Applicant: Vanguard International Semiconductor Corporation
    Inventors: Walter Wohlmuth, Shin-Cheng Lin, Chia-Ching Huang
  • Patent number: 7368980
    Abstract: An exemplary circuit embodiment includes a depletion-mode transistor and an enhancement-mode transistor. The circuit also includes a circuit portion coupled to a gate region of the depletion-mode transistor and to a gate region of the enhancement-mode transistor. In this embodiment, the circuit portion is configured to provide a reference voltage at an output node, wherein the reference voltage is associated with a difference between a voltage at the gate region of the depletion-mode transistor and a voltage at the gate region of the enhancement-mode transistor.
    Type: Grant
    Filed: April 25, 2005
    Date of Patent: May 6, 2008
    Assignee: TriQuint Semiconductor, Inc.
    Inventors: Rebouh Benelbar, Walter Wohlmuth
  • Publication number: 20070023901
    Abstract: One embodiment of an integrated circuit includes a substrate, an electrical device positioned above the substrate, and a bond bad positioned above and aligned along a vertical axis with the electrical device such that the electrical device is positioned between the substrate and the bond pad.
    Type: Application
    Filed: July 29, 2005
    Publication date: February 1, 2007
    Inventors: Gerard Mahoney, Matthew Essar, Walter Wohlmuth, Wayne Struble
  • Publication number: 20060238234
    Abstract: An exemplary circuit embodiment includes a depletion-mode transistor and an enhancement-mode transistor. The circuit also includes a circuit portion coupled to a gate region of the depletion-mode transistor and to a gate region of the enhancement-mode transistor. In this embodiment, the circuit portion is configured to provide a reference voltage at an output node, wherein the reference voltage is associated with a difference between a voltage at the gate region of the depletion-mode transistor and a voltage at the gate region of the enhancement-mode transistor.
    Type: Application
    Filed: April 25, 2005
    Publication date: October 26, 2006
    Inventors: Rebouh Benelbar, Walter Wohlmuth
  • Publication number: 20060197129
    Abstract: One embodiment of a fin-field effect transistor includes a material stack including a non-inverting su surface channel, a fin of semiconductor material positioned on the material stack, the fin including first and second opposing side surfaces, and a gate electrode positioned on the first and second opposing side surfaces of the fin.
    Type: Application
    Filed: March 3, 2005
    Publication date: September 7, 2006
    Inventor: Walter Wohlmuth
  • Publication number: 20060027840
    Abstract: A depletion mode (D-mode) field effect transistor (FET) is monolithically integrated with an enhancement mode (E-mode) FET in a multi-layer structure. The multi-layer structure includes a channel layer overlaid by a barrier layer overlaid by an ohmic contact layer. Source and drain contacts of the D-mode and E-mode FETs are coupled to the ohmic contact layer. A gate contact of the D-mode and E-mode FETs is coupled to the barrier layer. An amorphized region is provided beneath the E-mode gate contact within the barrier layer. The amorphized region forms a buried E-mode Schottky contact with the barrier layer. An alternative embodiment couples the gate contact of the D-mode transistor to a first layer that overlies the barrier layer, and provides a similar D-mode amorphized region within the first layer.
    Type: Application
    Filed: October 11, 2005
    Publication date: February 9, 2006
    Applicant: TriQuint Semiconductor, Inc.
    Inventor: Walter Wohlmuth
  • Publication number: 20050110054
    Abstract: A depletion mode (D-mode) field effect transistor (FET) is monolithically integrated with an enhancement mode (E-mode) FET in a multi-layer structure. The multi-layer structure includes a channel layer overlaid by a barrier layer overlaid by an ohmic contact layer. Source and drain contacts of the D-mode and E-mode FETs are coupled to the ohmic contact layer. A gate contact of the D-mode and E-mode FETs is coupled to the barrier layer. An amorphized region is provided beneath the E-mode gate contact within the barrier layer. The amorphized region forms a buried E-mode Schottky contact with the barrier layer. An alternative embodiment couples the gate contact of the D-mode transistor to a first layer that overlies the barrier layer, and provides a similar D-mode amorphized region within the first layer.
    Type: Application
    Filed: November 24, 2003
    Publication date: May 26, 2005
    Inventor: Walter Wohlmuth
  • Patent number: 5880482
    Abstract: A low dark current metal-semiconductor-metal photodetector has an active region for receiving photons and generating charge carriers in the form of holes and electrons in response to the photons and an isolation region for allowing electrical coupling to occur without increasing the dark current. The photodetector is a III-V ternary semiconductor having its active region defined by a via through a dielectric layer. A pair of electrodes has contact portions extending into contact with the active region and terminating on the isolation region. One electrode of the pair provides a high Schottky barrier to holes.
    Type: Grant
    Filed: January 29, 1997
    Date of Patent: March 9, 1999
    Assignee: The Board of Trustees of the University of Illinios
    Inventors: Ilesanmi Adesida, Walter Wohlmuth, Mohamed Arafa, Patrick Fay