Abstract: Various embodiments of the present disclosure are directed towards a memory cell comprising a blocking layer configured to block diffusion of metal from an electrode of the memory cell to a ferroelectric layer of the memory cell. More particularly, the blocking layer and the ferroelectric layer are between a top electrode of the memory cell and a bottom electrode of the memory cell, which both comprise metal. Further, the blocking layer is between the ferroelectric layer and the electrode, which corresponds to one of the top and bottom electrodes. In some embodiments, the metal of the one of the top and bottom electrodes has a lowest electronegativity amongst the metals of top and bottom electrodes and is hence the most reactive and likely to diffuse amongst the metals of top and bottom electrodes.

Abstract: The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes a semiconductor substrate having sidewalls that define a recess within an upper surface of the semiconductor substrate. A plurality of upper electrode segments are arranged over the semiconductor substrate and are vertically separated from the upper surface of the semiconductor substrate by a first dielectric layer. A lower electrode segment is arranged directly between the sidewalls of the semiconductor substrate and directly between adjacent ones of the plurality of upper electrode segments. A second dielectric layer is arranged directly between the sidewalls of the semiconductor substrate and the lower electrode segment and also directly between the plurality of upper electrode segments and the lower electrode segment.

Abstract: Various embodiments of the present disclosure are directed towards methods for forming conductive lines and conductive sockets using mandrels with turns, as well as the resulting conductive lines and sockets. A conductive socket of the present disclosure may have a top layout with at least one turn and with a width that is substantially the same as that of conductive lines along the at least one turn. Such a top layout may reduce loading during formation of the conductive socket. Conductive lines of the present disclosure may comprise outer conductive lines and inner conductive lines having ends laterally offset from ends of the outer conductive lines along lengths of the conductive lines. Formation of the inner and outer conductive lines using a mandrel with a turn may enlarge a process window while cutting ends of a sidewall spacer structure from which the inner and outer conductive lines are formed.

Abstract: The present invention discloses a system and a method of walkie-talkie communication crossing various wireless frequency domains. The system includes walkie-talkies, communication servers, and a connection network connecting the communication servers for mutual communication. The walkie-talkies are divided into communication groups, and each communication group is assigned to one specific communication server. The walkie-talkies and the communication server in the same communication group employ an exclusive wireless channel to wirelessly communicate. In particular, the communication server is invoked by one of the walkie-talkies in the same communication group to perform a broadcasting process for the walkie-talkies in different communication groups to broadcast at the same time. The present invention is suitably applied to any indoor or outdoor environments as long as the communication servers are provided.

Abstract: The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes a semiconductor substrate having sidewalls that define a recess within an upper surface of the semiconductor substrate. A plurality of upper electrode segments are arranged over the semiconductor substrate and are vertically separated from the upper surface of the semiconductor substrate by a first dielectric layer. A lower electrode segment is arranged directly between the sidewalls of the semiconductor substrate and directly between adjacent ones of the plurality of upper electrode segments. A second dielectric layer is arranged directly between the sidewalls of the semiconductor substrate and the lower electrode segment and also directly between the plurality of upper electrode segments and the lower electrode segment.

Abstract: The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes a plurality of upper electrodes disposed over a substrate and a lower electrode disposed between the plurality of upper electrodes. A charge storage layer continuously extends from along a first side of the lower electrode to along a second side of the lower electrode opposing the first side. The charge storage layer separates the lower electrode from the plurality of upper electrodes and the substrate. A silicide is disposed over the lower electrode and the plurality of upper electrodes. The silicide has sidewalls that are laterally separated by a distance directly overlying a top of the charge storage layer.

Abstract: The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes a plurality of upper electrodes disposed over a substrate and a lower electrode disposed between the plurality of upper electrodes. A charge storage layer continuously extends from along a first side of the lower electrode to along a second side of the lower electrode opposing the first side. The charge storage layer separates the lower electrode from the plurality of upper electrodes and the substrate. A silicide is disposed over the lower electrode and the plurality of upper electrodes. The silicide has sidewalls that are laterally separated by a distance directly overlying a top of the charge storage layer.

Abstract: A method for using an intercom to implement an intelligent calling process, an intelligent calling apparatus and a system is presented. The method is adapted to a site that adopts intercoms to perform a calling process. The system utilizes a server for receiving a calling signal generated by an intelligent calling apparatus. The calling signal records ID information used to represent a calling location. The server obtains the calling location by querying a database. The software process running in the server combines voice signals according to the calling location. A calling voice is generated and sent to the intercoms carried by the personnel member. When any personnel members receive the calling voice by the intercom, this calling process can be completed as the personnel member arrives at the calling location.

Abstract: The disclosure is related to an IoT service system with a Bluetooth Low Energy mesh network, and a communication method thereof. The IoT service system includes multiple intelligent service calling devices, multiple service communication devices and an agent node forming a BLE mesh network. One service calling device generates a service request signal that is broadcasted over a BLE mesh network. When a server receives the service request signal through the agent node, a service personnel and his portable service communication device are obtained by querying a database according to identification information relating to the service calling device that generates the service request signal. A service calling signal is therefore formed and broadcasted over the BLE mesh network. If a distance between the service communication device and the service calling device reaches a threshold while the service personnel is in service, a service dismissing signal is generated.

Abstract: The disclosure is related to a method for intelligent calling service, an apparatus and a system thereof. The method is performed in a server. When the server receives a service request signal recording a device ID generated by an apparatus for intelligent calling service, call information of service personnel can be obtained based on a service location corresponding to the device ID by querying a database of the server. After that, the server issues a service call signal to service communication devices carried by the service personnel. When a distance between the service communication device and the apparatus for intelligent calling service reaches a threshold, it shows that one of the service personnel is in service. This calling service procedure is done when the server receives a dismissing signal generated by the apparatus or the service communication device near the apparatus.

Abstract: The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes a plurality of upper electrodes separated from a semiconductor substrate by a first dielectric layer. A lower electrode is laterally disposed between the plurality of upper electrodes and between sidewalls of the semiconductor substrate. A second dielectric layer lines opposing sidewalls and a lower surface of the lower electrode. The second dielectric layer laterally separates the lower electrode from the plurality of upper electrodes and from the sidewalls of the semiconductor substrate.

Abstract: A walkie-talkie messaging system includes a processing controller device, a sensing signal transmission unit, a master walkie-talkie, and a plurality of slave walkie-talkies. The sensing signal transmission unit is connected to the processing controller device via a wired or wireless connection, the processing controller device is connected to the master walkie-talkie via a wired connection, and the master walkie-talkie is connected to the slave walkie-talkies via a wireless connection. The processing controller device further includes a comparison module, a database, a determination module and a schedule module. The database is connected to the comparison module and the determination module, and the determination module is connected to the schedule module. The master walkie-talkie is connected to the processing controller device via an audio line, such that the processing controller device is capable of determining whether the master walkie-talkie is occupied by an activity.

Abstract: The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes a plurality of upper electrodes separated from a semiconductor substrate by a first dielectric layer. A lower electrode is laterally disposed between the plurality of upper electrodes and between sidewalls of the semiconductor substrate. A second dielectric layer lines opposing sidewalls and a lower surface of the lower electrode. The second dielectric layer laterally separates the lower electrode from the plurality of upper electrodes and from the sidewalls of the semiconductor substrate.

Abstract: The present disclosure relates to an integrated chip having an inter-digitated capacitor, and an associated method of formation. In some embodiments, the integrated chip has a plurality of upper electrodes separated from a substrate by a first dielectric layer. A plurality of lower electrodes vertically extend from between the plurality of upper electrodes to locations embedded within the substrate. A charge trapping dielectric layer is arranged between the substrate and the plurality of lower electrodes and between the plurality of upper electrodes and the plurality of lower electrodes. The charge trapping dielectric layer has a plurality of discrete segments respectively lining opposing sidewalls and a lower surface of one of the plurality of lower electrodes.

Abstract: An antibody, or a binding fragment of the antibody, against H1N1 virus, includes a heavy chain variable region and a light chain variable region, wherein the heavy chain variable region contains complementarity determining regions (CDR) that have the amino acid sequences of SEQ ID NO: 5, SEQ ID NO: 6, and SEQ ID NO: 7; and wherein the light chain variable region contains complementarity determining regions that have the amino acid sequences of SEQ ID NO: 8, SEQ ID NO: 9, and SEQ ID NO: 10. A method for treating or preventing H1N1 infection in a subject includes administering to the subject the antibody or the binding fragment of the antibody.

Abstract: The present disclosure relates to an integrated chip having an inter-digitated capacitor, and an associated method of formation. In some embodiments, the integrated chip has a plurality of upper electrodes separated from a substrate by a first dielectric layer. A plurality of lower electrodes vertically extend from between the plurality of upper electrodes to locations embedded within the substrate. A charge trapping dielectric layer is arranged between the substrate and the plurality of lower electrodes and between the plurality of upper electrodes and the plurality of lower electrodes. The charge trapping dielectric layer has a plurality of discrete segments respectively lining opposing sidewalls and a lower surface of one of the plurality of lower electrodes.

Abstract: The present disclosure relates to an inter-digitated capacitor that can be formed along with split-gate flash memory cells and that provides for a high capacitance per unit area, and a method of formation. In some embodiments, the inter-digitated capacitor has a well region disposed within an upper surface of a semiconductor substrate. A plurality of trenches vertically extend from the upper surface of the semiconductor substrate to positions within the well region. Lower electrodes are arranged within the plurality of trenches. The lower electrodes are separated from the well region by a charge trapping dielectric layer arranged along inner-surfaces of the plurality of trenches. A plurality of upper electrodes are arranged over the semiconductor substrate at locations laterally separated from the lower electrodes by the charge trapping dielectric layer and vertically separated from the well region by a first dielectric layer.

Abstract: The present disclosure relates to an inter-digitated capacitor that can be formed along with split-gate flash memory cells and that provides for a high capacitance per unit area, and a method of formation. In some embodiments, the inter-digitated capacitor has a well region disposed within an upper surface of a semiconductor substrate. A plurality of trenches vertically extend from the upper surface of the semiconductor substrate to positions within the well region. Lower electrodes are arranged within the plurality of trenches. The lower electrodes are separated from the well region by a charge trapping dielectric layer arranged along inner-surfaces of the plurality of trenches. A plurality of upper electrodes are arranged over the semiconductor substrate at locations laterally separated from the lower electrodes by the charge trapping dielectric layer and vertically separated from the well region by a first dielectric layer.

Abstract: An antibody, or a binding fragment of the antibody, against H1N1 virus, includes a heavy chain variable region and a light chain variable region, wherein the heavy chain variable region contains complementarity determining regions (CDR) that have the amino acid sequences of SEQ ID NO: 5, SEQ ID NO: 6, and SEQ ID NO: 7; and wherein the light chain variable region contains complementarity determining regions that have the amino acid sequences of SEQ ID NO: 8, SEQ ID NO: 9, and SEQ ID NO: 10. A method for treating or preventing H1N1 infection in a subject includes administering to the subject the antibody or the binding fragment of the antibody.

Abstract: A method for controllable layer-by-layer removal of graphene layers is provided. The method includes the steps of: disposing a single-layer or multi-layer graphene on a heat source, arranging graphene layer or layers in a sealed chamber filled with ozone gas, and removing a targeted area of graphene with a laser. The method provides low-temperature removal of graphene layer-by-layer. The heat source, laser, and the highly oxidizing ozone gas selectively control the removal of graphene layers.