Abstract: A sealing structure includes a box body and a cover body. The box body includes a plurality of side walls respectively including a plurality of outer and inner portions, an annular groove formed on the inner portions, and an annular protrusion portion. Each outer portion has a level difference with the corresponding inner portion. Any two adjacent ones of the side walls form a corner portion. An outer surface of each corner portion forms a sharp corner. The annular groove is arc-shaped at a position corresponding to each corner portion. Each corner portion includes a hollowed-out area. The cover body includes a main body in a polygonal shape with sharp corners, an annular protrusion portion protruding from the main body, and an annular groove. The annular protrusion portions extend into the annular grooves, so that the cover body is sealedly joined to the box body.

Abstract: Various embodiments of the present disclosure are directed towards a memory cell comprising a blocking layer configured to block diffusion of metal from an electrode of the memory cell to a ferroelectric layer of the memory cell. More particularly, the blocking layer and the ferroelectric layer are between a top electrode of the memory cell and a bottom electrode of the memory cell, which both comprise metal. Further, the blocking layer is between the ferroelectric layer and the electrode, which corresponds to one of the top and bottom electrodes. In some embodiments, the metal of the one of the top and bottom electrodes has a lowest electronegativity amongst the metals of top and bottom electrodes and is hence the most reactive and likely to diffuse amongst the metals of top and bottom electrodes.

Abstract: Various embodiments of the present disclosure are directed towards a memory cell comprising a blocking layer configured to block diffusion of metal from an electrode of the memory cell to a ferroelectric layer of the memory cell. More particularly, the blocking layer and the ferroelectric layer are between a top electrode of the memory cell and a bottom electrode of the memory cell, which both comprise metal. Further, the blocking layer is between the ferroelectric layer and the electrode, which corresponds to one of the top and bottom electrodes. In some embodiments, the metal of the one of the top and bottom electrodes has a lowest electronegativity amongst the metals of top and bottom electrodes and is hence the most reactive and likely to diffuse amongst the metals of top and bottom electrodes.

Abstract: Various embodiments of the present disclosure are directed towards methods for forming conductive lines and conductive sockets using mandrels with turns, as well as the resulting conductive lines and sockets. A conductive socket of the present disclosure may have a top layout with at least one turn and with a width that is substantially the same as that of conductive lines along the at least one turn. Such a top layout may reduce loading during formation of the conductive socket. Conductive lines of the present disclosure may comprise outer conductive lines and inner conductive lines having ends laterally offset from ends of the outer conductive lines along lengths of the conductive lines. Formation of the inner and outer conductive lines using a mandrel with a turn may enlarge a process window while cutting ends of a sidewall spacer structure from which the inner and outer conductive lines are formed.

Abstract: Various embodiments of the present disclosure are directed towards methods for forming conductive lines and conductive sockets using mandrels with turns, as well as the resulting conductive lines and sockets. A conductive socket of the present disclosure may have a top layout with at least one turn and with a width that is substantially the same as that of conductive lines along the at least one turn. Such a top layout may reduce loading during formation of the conductive socket. Conductive lines of the present disclosure may comprise outer conductive lines and inner conductive lines having ends laterally offset from ends of the outer conductive lines along lengths of the conductive lines. Formation of the inner and outer conductive lines using a mandrel with a turn may enlarge a process window while cutting ends of a sidewall spacer structure from which the inner and outer conductive lines are formed.

Abstract: A memory device includes a two-dimensional array of access transistors located on a semiconductor substrate; metal interconnect structures embedded in dielectric material layers and electrical connected to electrical nodes of the access transistors; and a two-dimensional array of resistive memory structures embedded in the dielectric material layers. The metal interconnect structures include two first source lines located at a first metal line level and laterally extending along a first horizontal direction; a second source line located at a second metal line level and laterally extending along the first horizontal direction; and a vertical connection structure including a plurality of interconnection via structures and at least one line-level metal structure and providing a vertical electrical connection between the two first source lines and the second source line.

Abstract: A semiconductor device and a manufacturing method thereof are provided. The semiconductor device includes a top electrode layer, a bottom electrode layer, an insulator layer and a hard mask layer. The insulator layer is disposed between the top electrode layer and the bottom electrode. The top electrode layer, the insulator layer and the bottom electrode layer form a metal-insulator-metal structure. The hard mask layer stacks on the top electrode layer. The insulator layer protrudes from a first sidewall of the top electrode layer and a second sidewall of the bottom electrode layer.

Abstract: A sealing structure includes a box body and a cover body. The box body includes a plurality of side walls respectively including a plurality of outer and inner portions, an annular groove formed on the inner portions, and an annular protrusion portion. Each outer portion has a level difference with the corresponding inner portion. Any two adjacent ones of the side walls form a corner portion. An outer surface of each corner portion forms a sharp corner. The annular groove is arc-shaped at a position corresponding to each corner portion. Each corner portion includes a hollowed-out area. The cover body includes a main body in a polygonal shape with sharp corners, an annular protrusion portion protruding from the main body, and an annular groove. The annular protrusion portions extend into the annular grooves, so that the cover body is sealedly joined to the box body.

Abstract: A ferroelectric tunnel junction is formed, comprising a plurality of layers including at least a bottom electrode layer, a top electrode layer, and at least one ferroelectric layer disposed between the bottom electrode layer and the top electrode layer. The at least one ferroelectric layer comprises a ferroelectric material. At least one layer of the plurality of layers is in contact with the ferroelectric layer and has a coefficient of thermal expansion that is at least 25% lower than a coefficient of thermal expansion of the ferroelectric layer; and inducing ferroelectric phase crystallization in the ferroelectric layer by annealing the plurality of layers.

Abstract: Various embodiments of the present disclosure are directed towards a memory cell comprising a blocking layer configured to block diffusion of metal from an electrode of the memory cell to a ferroelectric layer of the memory cell. More particularly, the blocking layer and the ferroelectric layer are between a top electrode of the memory cell and a bottom electrode of the memory cell, which both comprise metal. Further, the blocking layer is between the ferroelectric layer and the electrode, which corresponds to one of the top and bottom electrodes. In some embodiments, the metal of the one of the top and bottom electrodes has a lowest electronegativity amongst the metals of top and bottom electrodes and is hence the most reactive and likely to diffuse amongst the metals of top and bottom electrodes.

Abstract: The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes a semiconductor substrate having sidewalls that define a recess within an upper surface of the semiconductor substrate. A plurality of upper electrode segments are arranged over the semiconductor substrate and are vertically separated from the upper surface of the semiconductor substrate by a first dielectric layer. A lower electrode segment is arranged directly between the sidewalls of the semiconductor substrate and directly between adjacent ones of the plurality of upper electrode segments. A second dielectric layer is arranged directly between the sidewalls of the semiconductor substrate and the lower electrode segment and also directly between the plurality of upper electrode segments and the lower electrode segment.

Abstract: Various embodiments of the present disclosure are directed towards methods for forming conductive lines and conductive sockets using mandrels with turns, as well as the resulting conductive lines and sockets. A conductive socket of the present disclosure may have a top layout with at least one turn and with a width that is substantially the same as that of conductive lines along the at least one turn. Such a top layout may reduce loading during formation of the conductive socket. Conductive lines of the present disclosure may comprise outer conductive lines and inner conductive lines having ends laterally offset from ends of the outer conductive lines along lengths of the conductive lines. Formation of the inner and outer conductive lines using a mandrel with a turn may enlarge a process window while cutting ends of a sidewall spacer structure from which the inner and outer conductive lines are formed.

Abstract: The present invention discloses a system and a method of walkie-talkie communication crossing various wireless frequency domains. The system includes walkie-talkies, communication servers, and a connection network connecting the communication servers for mutual communication. The walkie-talkies are divided into communication groups, and each communication group is assigned to one specific communication server. The walkie-talkies and the communication server in the same communication group employ an exclusive wireless channel to wirelessly communicate. In particular, the communication server is invoked by one of the walkie-talkies in the same communication group to perform a broadcasting process for the walkie-talkies in different communication groups to broadcast at the same time. The present invention is suitably applied to any indoor or outdoor environments as long as the communication servers are provided.

Abstract: The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes a semiconductor substrate having sidewalls that define a recess within an upper surface of the semiconductor substrate. A plurality of upper electrode segments are arranged over the semiconductor substrate and are vertically separated from the upper surface of the semiconductor substrate by a first dielectric layer. A lower electrode segment is arranged directly between the sidewalls of the semiconductor substrate and directly between adjacent ones of the plurality of upper electrode segments. A second dielectric layer is arranged directly between the sidewalls of the semiconductor substrate and the lower electrode segment and also directly between the plurality of upper electrode segments and the lower electrode segment.

Abstract: The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes a plurality of upper electrodes disposed over a substrate and a lower electrode disposed between the plurality of upper electrodes. A charge storage layer continuously extends from along a first side of the lower electrode to along a second side of the lower electrode opposing the first side. The charge storage layer separates the lower electrode from the plurality of upper electrodes and the substrate. A silicide is disposed over the lower electrode and the plurality of upper electrodes. The silicide has sidewalls that are laterally separated by a distance directly overlying a top of the charge storage layer.

Abstract: The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes a plurality of upper electrodes disposed over a substrate and a lower electrode disposed between the plurality of upper electrodes. A charge storage layer continuously extends from along a first side of the lower electrode to along a second side of the lower electrode opposing the first side. The charge storage layer separates the lower electrode from the plurality of upper electrodes and the substrate. A silicide is disposed over the lower electrode and the plurality of upper electrodes. The silicide has sidewalls that are laterally separated by a distance directly overlying a top of the charge storage layer.

Abstract: A method for using an intercom to implement an intelligent calling process, an intelligent calling apparatus and a system is presented. The method is adapted to a site that adopts intercoms to perform a calling process. The system utilizes a server for receiving a calling signal generated by an intelligent calling apparatus. The calling signal records ID information used to represent a calling location. The server obtains the calling location by querying a database. The software process running in the server combines voice signals according to the calling location. A calling voice is generated and sent to the intercoms carried by the personnel member. When any personnel members receive the calling voice by the intercom, this calling process can be completed as the personnel member arrives at the calling location.

Abstract: The disclosure is related to a method for intelligent calling service, an apparatus and a system thereof. The method is performed in a server. When the server receives a service request signal recording a device ID generated by an apparatus for intelligent calling service, call information of service personnel can be obtained based on a service location corresponding to the device ID by querying a database of the server. After that, the server issues a service call signal to service communication devices carried by the service personnel. When a distance between the service communication device and the apparatus for intelligent calling service reaches a threshold, it shows that one of the service personnel is in service. This calling service procedure is done when the server receives a dismissing signal generated by the apparatus or the service communication device near the apparatus.

Abstract: The disclosure is related to an IoT service system with a Bluetooth Low Energy mesh network, and a communication method thereof. The IoT service system includes multiple intelligent service calling devices, multiple service communication devices and an agent node forming a BLE mesh network. One service calling device generates a service request signal that is broadcasted over a BLE mesh network. When a server receives the service request signal through the agent node, a service personnel and his portable service communication device are obtained by querying a database according to identification information relating to the service calling device that generates the service request signal. A service calling signal is therefore formed and broadcasted over the BLE mesh network. If a distance between the service communication device and the service calling device reaches a threshold while the service personnel is in service, a service dismissing signal is generated.

Abstract: The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes a plurality of upper electrodes separated from a semiconductor substrate by a first dielectric layer. A lower electrode is laterally disposed between the plurality of upper electrodes and between sidewalls of the semiconductor substrate. A second dielectric layer lines opposing sidewalls and a lower surface of the lower electrode. The second dielectric layer laterally separates the lower electrode from the plurality of upper electrodes and from the sidewalls of the semiconductor substrate.