Abstract: A method and a User Equipment (UE) for beam operations are provided. The method includes monitoring at least one of a plurality of Control Resource Sets (CORESETs) configured for the UE within an active Bandwidth Part (BWP) of a serving cell in a time slot; and applying a first Quasi Co-Location (QCL) assumption of a first CORESET of a set of one or more of the monitored at least one of the plurality of CORESETs to receive a Downlink (DL) Reference Signal (RS), wherein the first CORESET is associated with a monitored search space configured with a lowest CORESET Identity (ID) among the set of one or more of the monitored at least one of the plurality of CORESETs.

Abstract: A method for wireless communication performed by a user equipment (UE) is provided. The method includes receiving, from a base station (BS), a Radio Resource Control (RRC) configuration to configure a first semi-persistent scheduling (SPS) physical downlink shared channel (PDSCH) and generating first uplink control information (UCI) in response to the first SPS PDSCH, where the RRC configuration includes a first parameter that indicates a priority of the first UCI.

Abstract: Some of the present implementations provide a method for a user equipment (UE) for receiving a power saving signal. The method receives, from a base station, a power saving signal comprising a minimum applicable K0 (K0min) that indicates a minimum scheduling offset restriction between a physical downlink control channel (PDCCH) and a physical downlink shared channel (PDSCH). The method determines an application delay based on a predefined value. The method then applies the minimum scheduling offset restriction after the application delay.

Abstract: A method for PDCCH monitoring performed by a UE is provided. The method includes performing the PDCCH monitoring in a first group associated with at least one first PDCCH monitoring configuration; receiving, from a base station, DCI comprising an indicator; performing the PDCCH monitoring in a second group associated with at least one second PDCCH monitoring configuration; and stopping the PDCCH monitoring in the first group after receiving the indicator.

Abstract: A conductive heat dissipating device for microcomputers includes a motherboard having an opening and a first electric connector installed adjacent to the front side of the opening, an adapter board having a second electric connector connected to the first electric connector on the front side of the opening, a processor soldered at the back of the adapter board or a third electric connector for inserting a processor, such that the processor is placed upside down into the opening, and a heat dissipating board connected to the back of the motherboard and in contact with the surface of the processor, and the heat dissipating board is in contact with a special heat dissipating structure in a chassis to define an external conductive heat dissipating device capable of dissipating the heat to the outside, reducing the size of the microcomputer, shortening the distance of thermal conduction, and improving the heat dissipation.

Abstract: A computer mainframe includes a housing, a motherboard, an intermediate circuit board, and a supporting bracket. A CD-ROM and a hard disk are attached to upper and lower sides, respectively, of the intermediate circuit board to sequentially superpose on and electrically connect to the motherboard via various connecting terminals provided at specific positions on the upper and the lower side of the intermediate circuit board. With the vertically superposed architecture of the mainframe, no space-occupying flat cable is needed for wiring the mainframe, enabling the mainframe to have a largely reduced volume.

Abstract: A computer mainframe includes a housing, a motherboard, an intermediate circuit board, and a supporting bracket. A CD-ROM and a hard disk are attached to upper and lower sides, respectively, of the intermediate circuit board to sequentially superpose on and electrically connect to the motherboard via various connecting terminals provided at specific positions on the upper and the lower side of the intermediate circuit board. With the vertically superposed architecture of the mainframe, no space-occupying flat cable is needed for wiring the mainframe, enabling the mainframe to have a largely reduced volume.