Abstract: A thin film transistor includes a semiconductor layer, a gate insulating layer, a gate, a source and a drain. The semiconductor layer has a first heavily doped region, a second heavily doped region, a third heavily doped region, an intrinsic region and a lightly doped region. The gate shields the intrinsic region and a first portion of the first heavily doped region. A second portion of the first heavily doped region is located outside an area of the gate. The source and the drain are electrically connected to the second heavily doped region and the third heavily doped region respectively. The source and the drain are arranged in a first direction. The first portion of the first heavily doped region and the gate have an overlapping region. A length of the overlapping region in the first direction is greater than a length of the intrinsic region in the first direction.

Abstract: A thin film transistor includes a buffer layer, a semiconductor layer, a gate dielectric layer, a first gate electrode, a source, and a drain. The buffer layer is disposed on the substrate. An upper surface of the buffer layer has a first surface, a second surface, a third surface, a fourth surface, and a fifth surface sequentially connected to form a recess. The semiconductor layer is disposed in the recess. The gate dielectric layer is disposed on the substrate, the semiconductor layer, and the buffer layer. The first gate is disposed on the gate dielectric layer and corresponds to the semiconductor layer. The source and the drain are disposed on the substrate and connected to the semiconductor layer. In addition, a manufacturing method of the thin film transistor and a control circuit including the thin film transistor are also provided.

Abstract: A thin film transistor includes a semiconductor layer, a gate insulating layer, a gate, a source and a drain. The semiconductor layer has a first heavily doped region, a second heavily doped region, a third heavily doped region, an intrinsic region and a lightly doped region. The gate shields the intrinsic region and a first portion of the first heavily doped region. A second portion of the first heavily doped region is located outside an area of the gate. The source and the drain are electrically connected to the second heavily doped region and the third heavily doped region respectively. The source and the drain are arranged in a first direction. The first portion of the first heavily doped region and the gate have an overlapping region. A length of the overlapping region in the first direction is greater than a length of the intrinsic region in the first direction.