Patents by Inventor Wan-Chun Huang
Wan-Chun Huang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11984485Abstract: A semiconductor device includes a substrate, a gate structure on the substrate, a source/drain (S/D) region and a contact. The S/D region is located in the substrate and on a side of the gate structure. The contact lands on and connected to the S/D region. The contact wraps around the S/D region.Type: GrantFiled: March 3, 2022Date of Patent: May 14, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Po-Hsien Cheng, Jr-Hung Li, Tai-Chun Huang, Tze-Liang Lee, Chung-Ting Ko, Jr-Yu Chen, Wan-Chen Hsieh
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Publication number: 20240145249Abstract: A device includes first and second gate structures respectively extending across the first and second fins, and a gate isolation plug between a longitudinal end of the first gate structure and a longitudinal end of the second gate structure. The gate isolation plug comprises a first dielectric layer and a second dielectric layer over the first dielectric layer. The first dielectric layer has an upper portion and a lower portion below the upper portion. The upper portion has a thickness smaller than a thickness of the lower portion of the first dielectric layer.Type: ApplicationFiled: March 24, 2023Publication date: May 2, 2024Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Ting-Gang CHEN, Wan Chen HSIEH, Bo-Cyuan LU, Tai-Jung KUO, Kuo-Shuo HUANG, Chi-Yen TUNG, Tai-Chun HUANG
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Patent number: 9471542Abstract: The present invention discloses a parameter generating device and the method thereof to generate a parameter for circuit operation in which the parameter corresponds to an N degree polynomial of a characteristic curve while said N is a positive integer. The parameter generating device comprises: a storage circuit to store at least N+1 initial values that are determined by a start value and a unit variation amount; and a parameter calculating circuit, coupled to the storage circuit, to carry out addition calculation for at least [(K?1)×N+1] time(s) if a multiple K is positive or subtraction calculation for at least ?K×N time(s) if the multiple K is negative, so as to generate the aforementioned parameter, wherein the multiple K is derived from a difference divided by the unit variation amount while the difference is a current value minus the start value.Type: GrantFiled: July 3, 2014Date of Patent: October 18, 2016Assignee: REALTEK SEMICONDUCTOR CORPORATIONInventors: Ching-Yao Su, Liang-Wei Huang, Shih-Wei Wang, Wan-Chun Huang
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Patent number: 9093611Abstract: An LED chip is disclosed. The LED chip includes a substrate and a semiconductor element formed on the substrate. A recess is formed on the semiconductor element so as to expose a first-type of semiconductor layer thereof to the environment. The LED chip also includes a conductive layer disposed on a second-type semiconductor layer of the semiconductor element, a first electrode disposed in the recess and electrically connected to the first-type of semiconductor layer, and a second electrode disposed on the conductive layer. In addition, the LED chip includes a first circular electrode disposed on the conductive layer and extending along an edge of the substrate and electrically connected to the second electrode.Type: GrantFiled: June 16, 2014Date of Patent: July 28, 2015Assignee: Lextar Electronics CorporationInventors: Wan-Chun Huang, Wei-Chang Yu
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Publication number: 20150069451Abstract: An LED chip is disclosed. The LED chip includes a substrate and a semiconductor element formed on the substrate. A recess is formed on the semiconductor element so as to expose a first-type of semiconductor layer thereof to the environment. The LED chip also includes a conductive layer disposed on a second-type semiconductor layer of the semiconductor element, a first electrode disposed in the recess and electrically connected to the first-type of semiconductor layer, and a second electrode disposed on the conductive layer. In addition, the LED chip includes a first circular electrode disposed on the conductive layer and extending along an edge of the substrate and electrically connected to the second electrode.Type: ApplicationFiled: June 16, 2014Publication date: March 12, 2015Inventors: Wan-Chun HUANG, Wei-Chang YU
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Patent number: 8975234Abstract: A method of inhibiting the growth of Gram-positive bacteria comprising administering an effective amount of Tellimagrandin II, its pharmaceutically acceptable salt, enantiomer, isomer or tautomer to a subject is provided. The Gram-positive bacteria comprise methicillin-resistant Staphylococcus aureus. A method of treating sepsis comprising administering an effective amount of Tellimagrandin II, its pharmaceutically acceptable salt, enantiomer, isomer or tautomer to a subject is also provided. A method of treating leukemia comprising administering an effective amount of Tellimagrandin II, its pharmaceutically acceptable salt, enantiomer, isomer or tautomer to a subject is further provided.Type: GrantFiled: January 20, 2012Date of Patent: March 10, 2015Assignee: Kaohsiung Medical UniversityInventors: Lih-Geeng Chen, Yen-Hsu Chen, Chin Hsu, Hsin-Ju Chien, Shih-Han Kao, Yu-Wei Chang, Wan-Chun Huang
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Publication number: 20150052181Abstract: The present invention discloses a parameter generating device and the method thereof to generate a parameter for circuit operation in which the parameter corresponds to an N degree polynomial of a characteristic curve while said N is a positive integer. The parameter generating device comprises: a storage circuit to store at least N+1 initial values that are determined by a start value and a unit variation amount; and an parameter calculating circuit, coupled to the storage circuit, to carry out addition calculation for at least [(K?1)×N+1] time(s) if a multiple K is positive or subtraction calculation for at least ?K×N time(s) if the multiple K is negative, so as to generate the aforementioned parameter, wherein the multiple K is derived from a difference divided by the unit variation amount while the difference is a current value minus the start value.Type: ApplicationFiled: July 3, 2014Publication date: February 19, 2015Inventors: Ching-Yao Su, Liang-Wei Huang, Shih-Wei Wang, Wan-Chun Huang
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Publication number: 20140231831Abstract: The invention provides a substrate structure used for manufacturing a light-emitting diode and a method for manufacturing the light-emitting diode. The substrate structure includes a substrate having a first surface and a second surface opposite to the first surface and a plurality of grooving structure formed on the first surface of the substrate. The light-emitting diode is formed on the first surface of the substrate.Type: ApplicationFiled: September 17, 2013Publication date: August 21, 2014Applicant: Lextar Electronics CorporationInventors: PEI-SHIU TSAI, Wan-Chun HUANG
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Publication number: 20120190632Abstract: A method of inhibiting the growth of Gram-positive bacteria comprising administering an effective amount of Tellimagrandin II, its pharmaceutically acceptable salt, enantiomer, isomer or tautomer to a subject is provided. The Gram-positive bacteria comprise methicillin-resistant Staphylococcus aureus. A method of treating sepsis comprising administering an effective amount of Tellimagrandin II, its pharmaceutically acceptable salt, enantiomer, isomer or tautomer to a subject is also provided. A method of treating leukemia comprising administering an effective amount of Tellimagrandin II, its pharmaceutically acceptable salt, enantiomer, isomer or tautomer to a subject is further provided.Type: ApplicationFiled: January 20, 2012Publication date: July 26, 2012Applicant: KAOHSIUNG MEDICAL UNIVERSITYInventors: Lih-Geeng Chen, Yen-Hsu Chen, Chin Hsu, Hsin-Ju Chien, Shih-Han Kao, Yu-Wei Chang, Wan-Chun Huang