Abstract: A physical unclonable function (PUF) generator including a substrate and semiconductor units is provided. Each of the semiconductor units includes an isolation structure, a first conductive line, and a second conductive line. The isolation structure is located in the substrate. The isolation structure has a first protrusion portion and a recess. The first protrusion portion and the recess are adjacent to each other. The first conductive line is located above the first protrusion portion and the recess. The second conductive line is located above the first conductive line. At least one short circuit randomly exists between at least one of the first conductive lines and at least one of the second conductive lines in at least one of the semiconductor units.

Abstract: A method of forming a flash memory cell includes the following steps. A first dielectric layer and a floating gate layer are deposited on a substrate sequentially. Three blocking structures having oblique sidewalls broaden from bottom to top penetrating through the first dielectric layer and the floating gate layer are formed. A first part and a second part of the floating gate layer between two adjacent blocking structures are etched respectively, so that a first floating gate having two sharp top corners and oblique sidewalls, and a second floating gate having two sharp top corners and oblique sidewalls, are formed. The three blocking structures are removed. A first isolating layer and a first selective gate covering the first floating gate are formed and a second isolating layer and a second selective gate covering the second floating gate are formed. A flash memory cell formed by said method is also provided.

Abstract: A method of forming a flash memory cell includes the following steps. A first dielectric layer and a floating gate layer are deposited on a substrate sequentially. Three blocking structures having oblique sidewalls broaden from bottom to top penetrating through the first dielectric layer and the floating gate layer are formed. A first part and a second part of the floating gate layer between two adjacent blocking structures are etched respectively, so that a first floating gate having two sharp top corners and oblique sidewalls, and a second floating gate having two sharp top corners and oblique sidewalls, are formed. The three blocking structures are removed. A first isolating layer and a first selective gate covering the first floating gate are formed and a second isolating layer and a second selective gate covering the second floating gate are formed. A flash memory cell formed by said method is also provided.

Abstract: The present application discloses a semiconductor structure and a manufacturing method thereof. The semiconductor structure comprises a substrate, a gate dielectric layer, a floating gate, a first dielectric layer and a control gate. The gate dielectric layer is disposed on the substrate. The floating gate is disposed on the gate dielectric layer and has at least one tip on a top surface of the floating gate. The first dielectric layer is disposed on the floating gate. The control gate is disposed above the first dielectric layer and at least partially overlaps the floating gate.

Abstract: A method of forming a flash memory cell includes the following steps. A first dielectric layer and a floating gate layer are deposited on a substrate sequentially. Three blocking structures having oblique sidewalls broaden from bottom to top penetrating through the first dielectric layer and the floating gate layer are formed. A first part and a second part of the floating gate layer between two adjacent blocking structures are etched respectively, so that a first floating gate having two sharp top corners and oblique sidewalls, and a second floating gate having two sharp top corners and oblique sidewalls, are formed. The three blocking structures are removed. A first isolating layer and a first selective gate covering the first floating gate are formed and a second isolating layer and a second selective gate covering the second floating gate are formed. A flash memory cell formed by said method is also provided.

Abstract: A method of forming a flash memory cell includes the following steps. A first dielectric layer and a floating gate layer are deposited on a substrate sequentially. Three blocking structures having oblique sidewalls broaden from bottom to top penetrating through the first dielectric layer and the floating gate layer are formed. A first part and a second part of the floating gate layer between two adjacent blocking structures are etched respectively, so that a first floating gate having two sharp top corners and oblique sidewalls, and a second floating gate having two sharp top corners and oblique sidewalls, are formed. The three blocking structures are removed. A first isolating layer and a first selective gate covering the first floating gate are formed and a second isolating layer and a second selective gate covering the second floating gate are formed. A flash memory cell formed by said method is also provided.

Abstract: A device for generating a security key includes a substrate, semiconductor units, contact structures, and defects. The semiconductor units are disposed on the substrate. The contact structures are disposed on and connected with the semiconductor units. The defects are disposed in at least a part of the contact structures randomly. A manufacturing method of a device for generating a security key includes the following steps. First semiconductor units are formed on a substrate. First contact structures are formed on the first semiconductor units. The first contact structures are connected with the first semiconductor units, and defects are formed in at least a part of the first contact structures randomly.

Abstract: The present application discloses a semiconductor structure and a manufacturing method thereof. The semiconductor structure comprises a substrate, a gate dielectric layer, a floating gate, a first dielectric layer and a control gate. The gate dielectric layer is disposed on the substrate. The floating gate is disposed on the gate dielectric layer and has at least one tip on a top surface of the floating gate. The first dielectric layer is disposed on the floating gate. The control gate is disposed above the first dielectric layer and at least partially overlaps the floating gate.

Abstract: A device for generating a security key includes a substrate, semiconductor units, contact structures, and defects. The semiconductor units are disposed on the substrate. The contact structures are disposed on and connected with the semiconductor units. The defects are disposed in at least a part of the contact structures randomly. A manufacturing method of a device for generating a security key includes the following steps. First semiconductor units are formed on a substrate. First contact structures are formed on the first semiconductor units. The first contact structures are connected with the first semiconductor units, and defects are formed in at least a part of the first contact structures randomly.

Abstract: Systems and apparatus for tracking tools are disclosed. In one embodiment, among others, an apparatus has a tool cabinet with at least one bin. A computing device is associated with the tool cabinet. A sensor network layer is positioned in the at least one bin. The sensor network is coupled with the computing device. The sensor network layer is configured to detect a presence and an absence of a tool item at a predetermined location. The sensor network is configured to transmit a signal to the computing device indicative of the presence or the absence of the tool item at the predetermined location. A covering positioned over the sensor network layer. The covering is configured to facilitate a placement of the tool item at the predetermined location.

Abstract: Systems and apparatus for tracking tools are disclosed. In one embodiment, among others, an apparatus has a tool cabinet with at least one bin. A computing device is associated with the tool cabinet. A sensor network layer is positioned in the at least one bin. The sensor network is coupled with the computing device. The sensor network layer is configured to detect a presence and an absence of a tool item at a predetermined location. The sensor network is configured to transmit a signal to the computing device indicative of the presence or the absence of the tool item at the predetermined location. A covering positioned over the sensor network layer. The covering is configured to facilitate a placement of the tool item at the predetermined location.

Abstract: Disclosed are various embodiments for automated tracking of inventory levels in storage bins. In one embodiment, among others, an adjustable bin divider may comprise a supporting base that has a receiving slot at an end, the receiving slot comprising a slide channel that extends along a top portion of the supporting base; a radio frequency identification (RFID) tag that is attached to the supporting base; and a radio frequency (RF)-blocking slide divider that comprises a first panel with an RF shield and a second panel that has a narrowed end, the first panel being connected to the second panel at the narrowed end, the first panel being inserted in the receiving slot, the narrowed end fitting within the slide channel of the receiving slot, wherein the RF-blocking slide divider conceals the RFID tag from detection from an RFID reader at a position along the slide channel.

Abstract: A method for fabricating a semiconductor integrated circuit (IC) having a SONOS memory device and a logic/analog device requiring different gate oxide layers comprises steps as follows: A substrate having a high voltage region, a memory region and a logic/analog is firstly provided. Next, a first gate oxide layer is formed on the high voltage region, the memory region and the logic/analog. The first gate oxide layer is then patterned to expose the logic/analog region and to define a first channel area and a second channel area respectively on the memory region and the high voltage region. Subsequently, a silicon oxide-silicon nitride-silicon oxide (ONO) structure is formed on the first channel area. A second gate oxide layer is then formed on the logic/analog and patterned to define a third channel area.

Abstract: A method for fabricating a semiconductor integrated circuit (IC) having a SONOS memory device and a logic/analog device requiring different gate oxide layers comprises steps as follows: A substrate having a high voltage region, a memory region and a logic/analog is firstly provided. Next, a first gate oxide layer is formed on the high voltage region, the memory region and the logic/analog. The first gate oxide layer is then patterned to expose the logic/analog region and to define a first channel area and a second channel area respectively on the memory region and the high voltage region. Subsequently, a silicon oxide-silicon nitride-silicon oxide (ONO) structure is formed on the first channel area. A second gate oxide layer is then formed on the logic/analog and patterned to define a third channel area.

Abstract: A touch communications device includes a first touch panel and a processor. The first touch panel includes a first region and a second region. The processor is arranged to control the first region and/or the second region to transmit a signal when a second touch panel of another touch communications device is close to or in contact with the first touch panel.

Abstract: Disclosed are various embodiments for automated tracking of inventory levels in storage bins. In one embodiment, among others, an adjustable bin divider may comprise a supporting base that has a receiving slot at an end, the receiving slot comprising a slide channel that extends along a top portion of the supporting base; a radio frequency identification (RFID) tag that is attached to the supporting base; and a radio frequency (RF)-blocking slide divider that comprises a first panel with an RF shield and a second panel that has a narrowed end, the first panel being connected to the second panel at the narrowed end, the first panel being inserted in the receiving slot, the narrowed end fitting within the slide channel of the receiving slot, wherein the RF-blocking slide divider conceals the RFID tag from detection from an RFID reader at a position along the slide channel.

Abstract: A touch communications device includes a first touch panel and a processor. The first touch panel includes a first region and a second region. The processor is arranged to control the first region and/or the second region to transmit a signal when a second touch panel of another touch communications device is close to or in contact with the first touch panel.

Abstract: A method for performing touch communications control and an associated apparatus are provided, where the method includes the steps of: performing communications to establish at least one communications connection between the touch communications device and a plurality of touch communications devices; obtaining identification information of each touch communications device of the plurality of touch communications devices to determine whether each touch communications device of the plurality of touch communications devices is one of a plurality of predetermined touch communications devices; and performing a predetermined action based on whether each touch communications device of the plurality of touch communications devices is one of the plurality of predetermined touch communications devices.

Abstract: A method of configuring permission for sharing data and touch link electronic device utilizing the same are described. The method, configuring permission for sharing data, adopted by a first touch link electronic device, the method including: establishing, by a touch panel of the first touch link electronic device, a first communication channel to a second touch link electronic device; transmitting the permission to the second touch link electronic device via the first communication channel, wherein the permission corresponds to the shared data; and transmitting the shared data to the second touch link electronic device.

Abstract: A touch communications device includes a first touch panel and a processor. When a second touch panel of another touch communications device is close to or in contact with the first touch panel of the touch communications device, the processor obtains relative movement information about a relative movement between the touch communications device and the other touch communications device. The processor executes a corresponding action according to the relative movement information.