Abstract: Disclosed is a method of forming a semiconductor device. The method includes providing a precursor having a substrate and protrusions over the substrate. The protrusions are interposed by trenches. The method further includes depositing a first dielectric layer over the protrusions and filling the trenches. The first dielectric layer has a first hardness. The method further includes treating the first dielectric layer with an oxidizer. The method further includes performing a chemical mechanical planarization (CMP) process to the first dielectric layer.

Abstract: A method of operating a chemical mechanical planarization (CMP) tool includes attaching a polishing pad to a first surface of a platen of the CMP tool using a glue; removing the polishing pad from the platen, wherein after removing the polishing pad, residue portions of the glue remain on the first surface of the platen; identifying locations of the residue portions of the glue on the first surface of the platen using a fluorescent material; and removing the residue portions of the glue from the first surface of the platen.

Abstract: A method of operating a chemical mechanical planarization (CMP) tool includes attaching a polishing pad to a first surface of a platen of the CMP tool using a glue; removing the polishing pad from the platen, wherein after removing the polishing pad, residue portions of the glue remain on the first surface of the platen; identifying locations of the residue portions of the glue on the first surface of the platen using a fluorescent material; and removing the residue portions of the glue from the first surface of the platen.

Abstract: A method of operating a chemical mechanical planarization (CMP) tool includes attaching a polishing pad to a first surface of a platen of the CMP tool using a glue; removing the polishing pad from the platen, wherein after removing the polishing pad, residue portions of the glue remain on the first surface of the platen; identifying locations of the residue portions of the glue on the first surface of the platen using a fluorescent material; and removing the residue portions of the glue from the first surface of the platen.

Abstract: Disclosed is a method of forming a semiconductor device. The method includes providing a precursor having a substrate and protrusions over the substrate. The protrusions are interposed by trenches. The method further includes depositing a first dielectric layer over the protrusions and filling the trenches. The first dielectric layer has a first hardness. The method further includes treating the first dielectric layer with an oxidizer. The method further includes performing a chemical mechanical planarization (CMP) process to the first dielectric layer.

Abstract: Disclosed is a method of forming a semiconductor device. The method includes providing a precursor having a substrate and protrusions over the substrate. The protrusions are interposed by trenches. The method further includes depositing a first dielectric layer over the protrusions and filling the trenches. The first dielectric layer has a first hardness. The method further includes treating the first dielectric layer with an oxidizer. The method further includes performing a chemical mechanical planarization (CMP) process to the first dielectric layer.

Abstract: Disclosed is a method of forming a semiconductor device. The method includes providing a precursor having a substrate and protrusions over the substrate. The protrusions are interposed by trenches. The method further includes depositing a first dielectric layer over the protrusions and filling the trenches. The first dielectric layer has a first hardness. The method further includes treating the first dielectric layer with an oxidizer. The method further includes performing a chemical mechanical planarization (CMP) process to the first dielectric layer.

Abstract: System and method for CMP station cleanliness. An embodiment comprises a chemical mechanical polishing (CMP) station comprising a housing unit covering the various components of the CMP station. The CMP station further comprising various surfaces of a slurry arm shield, a slurry spray nozzle, a pad conditioning arm shield, a platen shield, a carrier head; and the interior, vertical surfaces of the housing unit. A cleaning liquid delivery system configured to dose a cleaning liquid on the various surfaces of the CMP station at set intervals.

Abstract: Semiconductor devices and methods of manufacture thereof are disclosed. In some embodiments, a method of manufacturing a semiconductor device includes providing a workpiece including an n-type field effect transistor (N-FET) region, a p-type FET (P-FET) region, and an insulating material disposed over the N-FET region and the P-FET region. The method includes patterning the insulating material to expose a portion of the N-FET region and a portion of the P-FET region, and forming an oxide layer over the exposed portion of the N-FET region and the exposed portion of the P-FET region. The oxide layer over the P-FET region is altered, and a metal layer is formed over a portion of the N-FET region and the P-FET region. The workpiece is annealed to form a metal-insulator-semiconductor (MIS) tunnel diode over the N-FET region and a silicide or germinide material over the P-FET region.

Abstract: A semiconductor device may include a fin disposed over a workpiece. The fin may include: a first semiconductive material disposed over the workpiece; an oxide of the first semiconductive material disposed over the first semiconductive material; a second conductive material disposed over and spaced apart from the oxide of the first semiconductive material; a first insulating material disposed around and lining the second semiconductive material; a conductive material disposed around the first insulating material; and a second insulating material disposed between the oxide of the first semiconductive material and a portion of the conductive material facing the workpiece, the second insulating material further lining sidewalls of the conductive material.

Abstract: A method and apparatus for forming a CMOS device are provided. The CMOS device may include an N-type channel region formed of an III-V material and a P-type channel region formed of a germanium material. Over each channel may be formed corresponding gates and source/drain regions. The source/drain regions may be formed of a germanium material and one or more metallization layers. An anneal may be performed to form ohmic contacts for the source/drain regions. Openings may be formed in a dielectric layer covering the device and conductive plugs may be formed to provide contact to the source/drain regions.

Abstract: Methods for an oxide layer over an epitaxial layer. In an embodiment, a method includes forming an epitaxial layer of semiconductor material over a semiconductor substrate; forming an oxide layer over the epitaxial layer; applying a solution including an oxidizer to the oxide layer; and cleaning the oxide layer with a cleaning solution. In another embodiment, a densification process is applied to an oxide layer including treating with thermal energy, UV energy, or both. In an embodiment for a gate-all-around device, the cleaning process is applied to an oxide layer over an epitaxial portion of a fin. Additional methods are disclosed.

Abstract: A semiconductor device may include a fin disposed over a workpiece. The fin may include: a first semiconductive material disposed over the workpiece; an oxide of the first semiconductive material disposed over the first semiconductive material; a second conductive material disposed over and spaced apart from the oxide of the first semiconductive material; a first insulating material disposed around and lining the second semiconductive material; a conductive material disposed around the first insulating material; and a second insulating material disposed between the oxide of the first semiconductive material and a portion of the conductive material facing the workpiece, the second insulating material further lining sidewalls of the conductive material.

Abstract: Semiconductor devices and methods of manufacture thereof are disclosed. In some embodiments, a method of manufacturing a semiconductor device includes partially manufacturing a fin field effect transistor (FinFET) including a semiconductor fin comprising a first semiconductive material and a second semiconductive material disposed over the first semiconductive material. A top portion of the second semiconductive material of the semiconductor fin is removed, and a top portion of the first semiconductive material is exposed. A top portion first semiconductive material is removed from beneath the second semiconductive material. The first semiconductive material and the second semiconductive material are oxidized, forming a first oxide comprising a first thickness on the first semiconductive material and a second oxide comprising a second thickness on the second semiconductive material, the first thickness being greater than the second thickness.

Abstract: A method includes performing a first planarization step to remove portions of a semiconductor region over isolation regions. The first planarization step has a first selectivity, with the first selectivity being a ratio of a first removal rate of the semiconductor region to a second removal rate of the isolation regions. After the isolation regions are exposed, a second planarization step is performed on the isolation regions and a portion of the semiconductor region between the isolation regions. The second planarization step has a second selectivity lower than the first selectivity, with the second selectivity being a ratio of a third removal rate of the portion of semiconductor region to a fourth removal rate of the isolation regions.

Abstract: A method and apparatus for forming a CMOS device are provided. The CMOS device may include an N-type channel region formed of an III-V material and a P-type channel region formed of a germanium material. Over each channel may be formed corresponding gates and source/drain regions. The source/drain regions may be formed of a germanium material and one or more metallization layers. An anneal may be performed to form ohmic contacts for the source/drain regions. Openings may be formed in a dielectric layer covering the device and conductive plugs may be formed to provide contact to the source/drain regions.

Abstract: Methods for an oxide layer over an epitaxial layer. In an embodiment, a method includes forming an epitaxial layer of semiconductor material over a semiconductor substrate; forming an oxide layer over the epitaxial layer; applying a solution including an oxidizer to the oxide layer; and cleaning the oxide layer with a cleaning solution. In another embodiment, a densification process is applied to an oxide layer including treating with thermal energy, UV energy, or both. In an embodiment for a gate-all-around device, the cleaning process is applied to an oxide layer over an epitaxial portion of a fin. Additional methods are disclosed.

Abstract: Semiconductor devices and methods of manufacture thereof are disclosed. In some embodiments, a method of manufacturing a semiconductor device includes providing a workpiece including an n-type field effect transistor (N-FET) region, a p-type FET (P-FET) region, and an insulating material disposed over the N-FET region and the P-FET region. The method includes patterning the insulating material to expose a portion of the N-FET region and a portion of the P-FET region, and forming an oxide layer over the exposed portion of the N-FET region and the exposed portion of the P-FET region. The oxide layer over the P-FET region is altered, and a metal layer is formed over a portion of the N-FET region and the P-FET region. The workpiece is annealed to form a metal-insulator-semiconductor (MIS) tunnel diode over the N-FET region and a silicide or germinide material over the P-FET region.

Abstract: A method includes performing a first planarization step to remove portions of a semiconductor region over isolation regions. The first planarization step has a first selectivity, with the first selectivity being a ratio of a first removal rate of the semiconductor region to a second removal rate of the isolation regions. After the isolation regions are exposed, a second planarization step is performed on the isolation regions and a portion of the semiconductor region between the isolation regions. The second planarization step has a second selectivity lower than the first selectivity, with the second selectivity being a ratio of a third removal rate of the portion of semiconductor region to a fourth removal rate of the isolation regions.