Abstract: A touch detection module, includes: a plurality of driving electrodes arranged side by side; a plurality of sensing electrodes staggered with respect to the driving electrodes; and a touch driving circuit configured to supply touch driving signals to the plurality of driving electrodes and to detect touch detection signals through the plurality of sensing electrodes to identify touch position coordinates, wherein the touch driving circuit is configured: to vary frequency modulation parameter set values in response to a change in a frequency of reference clocks, and to generate and supply a frequency of the touch driving signals by using the reference clocks and a varied frequency modulation parameter set value.

Abstract: A semiconductor device is provided. The semiconductor device comprising a multi-channel active pattern on a substrate, a high dielectric constant insulating layer formed along the multi-channel active pattern on the multi-channel active pattern, wherein the high dielectric constant insulating layer comprises a metal, a silicon nitride layer formed along the high dielectric constant insulating layer on the high dielectric constant insulating layer and a gate electrode on the silicon nitride layer.

Abstract: A semiconductor device including: a first transistor which include a first gate stack on a substrate; and a second transistor which includes a second gate stack on the substrate, wherein the first gate stack includes a first ferroelectric material layer disposed on the substrate, a first work function layer disposed on the first ferroelectric material layer and a first upper gate electrode disposed on the first work function layer, wherein the second gate stack includes a second ferroelectric material layer disposed on the substrate, a second work function layer disposed on the second ferroelectric material layer and a second upper gate electrode disposed on the second work function layer, wherein the first work function layer includes the same material as the second work function layer, and wherein an effective work function of the first gate stack is different from an effective work function of the second gate stack.

Abstract: A printed circuit board (PCB) for reducing a size of a semiconductor package and a semiconductor package including the same are provided. The PCB includes a substrate base including a chip attach area disposed on a top thereof, a top pad and a bottom pad respectively disposed on the top and a bottom of the substrate base, a first top solder resist layer formed on the top of the substrate base and including a first pad opening corresponding to the top pad and covering the chip attach area, a second top solder resist layer formed on the first top solder resist layer and including a second pad opening corresponding to the top pad and a chip attach opening corresponding to the chip attach area, and a bottom solder resist layer formed on the bottom of the substrate base and including a third pad opening corresponding to the bottom pad.

Abstract: A printed circuit board (PCB) for reducing a size of a semiconductor package and a semiconductor package including the same are provided. The PCB includes a substrate base including a chip attach area disposed on a top thereof, a top pad and a bottom pad respectively disposed on the top and a bottom of the substrate base, a first top solder resist layer formed on the top of the substrate base and including a first pad opening corresponding to the top pad and covering the chip attach area, a second top solder resist layer formed on the first top solder resist layer and including a second pad opening corresponding to the top pad and a chip attach opening corresponding to the chip attach area, and a bottom solder resist layer formed on the bottom of the substrate base and including a third pad opening corresponding to the bottom pad.

Abstract: A stack package includes a substrate, a stack of semiconductor chips mounted to the substrate, a side semiconductor chip disposed on one side of the stack, and adhesive interposed between the lower surface of the side semiconductor chip and the stack of semiconductor chips and which attaches the side semiconductor chip to the stack.