Patents by Inventor Wan Hsuan Hsu
Wan Hsuan Hsu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11923199Abstract: Aspects of the disclosure provide a method. The method includes forming a structure over a substrate, and forming a spacer layer on the structure, wherein the spacer layer has a recess. The method includes forming a mask layer over the spacer layer and in the recess, the mask layer including a first layer, a second layer and a third layer. The method includes patterning the third layer of the mask layer, and etching the first layer and the second layer of the mask layer to form an opening to expose the recess of the spacer layer, wherein the opening in the second layer has a first width; and. The method includes removing the second layer using a wet etchant, wherein the opening in the third layer has a second width, and the second with is greater than the first width.Type: GrantFiled: June 21, 2022Date of Patent: March 5, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Nai-Chia Chen, Wan Hsuan Hsu, Chia-Wei Wu, Neng-Jye Yang, Chun-Li Chou
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Publication number: 20240021431Abstract: An apparatus, semiconductor device and method of manufacture are presented, wherein a hard mask layer and one or more etch stop layers are etched in an etching chamber. In an embodiment the semiconductor device is placed on a mounting platform at a first height and an etch process is performed, then the semiconductor device is moved to a second height within the chamber and a second etch process is performed, with the rotational speed of the semiconductor device reduced during movements in order to reduce the chance of cross contamination.Type: ApplicationFiled: July 28, 2023Publication date: January 18, 2024Inventors: Wan Hsuan Hsu, Jao Sheng Huang, Yen-Chiu Kuo, Yu-Li Cheng, Ya Tzu Chen, Neng-Jye Yang, Chun-Li Chou
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Patent number: 11776818Abstract: An apparatus, semiconductor device and method of manufacture are presented, wherein a hard mask layer and one or more etch stop layers are etched in an etching chamber. In an embodiment the semiconductor device is placed on a mounting platform at a first height and an etch process is performed, then the semiconductor device is moved to a second height within the chamber and a second etch process is performed, with the rotational speed of the semiconductor device reduced during movements in order to reduce the chance of cross contamination.Type: GrantFiled: April 19, 2021Date of Patent: October 3, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Wan Hsuan Hsu, Jao Sheng Huang, Yen-Chiu Kuo, Yu-Li Cheng, Ya Tzu Chen, Neng-Jye Yang, Chun-Li Chou
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Publication number: 20220319850Abstract: Aspects of the disclosure provide a method. The method includes forming a structure over a substrate, and forming a spacer layer on the structure, wherein the spacer layer has a recess. The method includes forming a mask layer over the spacer layer and in the recess, the mask layer including a first layer, a second layer and a third layer. The method includes patterning the third layer of the mask layer, and etching the first layer and the second layer of the mask layer to form an opening to expose the recess of the spacer layer, wherein the opening in the second layer has a first width; and. The method includes removing the second layer using a wet etchant, wherein the opening in the third layer has a second width, and the second with is greater than the first width.Type: ApplicationFiled: June 21, 2022Publication date: October 6, 2022Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Nai-Chia CHEN, Wan Hsuan HSU, Chia-Wei WU, Neng-Jye YANG, Chun-Li CHOU
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Patent number: 11398380Abstract: A middle layer removal method is provided. The method includes providing a substrate having a structure formed on the substrate, and forming a spacer layer on the structure. The method includes forming a mask layer over the spacer layer, the mask layer including a first layer, a second layer over the first layer, and a third layer over the second layer. The method also includes patterning the third layer of the mask layer, and etching the first layer and the second layer of the mask layer to form an opening to expose a bottom surface of the second layer. The method further includes removing the second layer using a wet etchant.Type: GrantFiled: May 8, 2020Date of Patent: July 26, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Nai-Chia Chen, Wan Hsuan Hsu, Chia-Wei Wu, Neng-Jye Yang, Chun-Li Chou
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Patent number: 11282750Abstract: An apparatus includes a first source and a common drain and on opposite sides of a first gate surrounded by a first gate spacer, a second source and the common drain on opposite sides of a second gate surrounded by a second gate spacer, a first protection layer formed along a sidewall of the first gate spacer, wherein a top surface of the first protection layer has a first slope, a second protection layer formed along a sidewall of the second gate spacer, wherein a top surface of the second protection layer has a second slope, a lower drain contact between the first gate and the second gate and an upper drain contact over the lower drain contact and between the first gate and the second gate, wherein at least a portion of the upper drain contact is in contact with the first slope and the second slope.Type: GrantFiled: September 3, 2020Date of Patent: March 22, 2022Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Wan Hsuan Hsu, I-Hsiu Wang, Yean-Zhaw Chen, Cheng-Wei Chang, Yu Shih Wang, Hsin-Yan Lu, Yi-Wei Chiu
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Publication number: 20210257218Abstract: An apparatus, semiconductor device and method of manufacture are presented, wherein a hard mask layer and one or more etch stop layers are etched in an etching chamber. In an embodiment the semiconductor device is placed on a mounting platform at a first height and an etch process is performed, then the semiconductor device is moved to a second height within the chamber and a second etch process is performed, with the rotational speed of the semiconductor device reduced during movements in order to reduce the chance of cross contamination.Type: ApplicationFiled: April 19, 2021Publication date: August 19, 2021Inventors: Wan Hsuan Hsu, Jao Sheng Huang, Yen-Chiu Kuo, Yu-Li Cheng, Ya Tzu Chen, Neng-Jye Yang, Chun-Li Chou
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Publication number: 20210118689Abstract: An apparatus, semiconductor device and method of manufacture are presented, wherein a hard mask layer and one or more etch stop layers are etched in an etching chamber. In an embodiment the semiconductor device is placed on a mounting platform at a first height and an etch process is performed, then the semiconductor device is moved to a second height within the chamber and a second etch process is performed, with the rotational speed of the semiconductor device reduced during movements in order to reduce the chance of cross contamination.Type: ApplicationFiled: October 18, 2019Publication date: April 22, 2021Inventors: Wan Hsuan Hsu, Jao Sheng Huang, Yen-Chiu Kuo, Yu-Li Cheng, Ya Tzu Chen, Neng-Jye Yang, Chun-Li Chou
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Patent number: 10985028Abstract: An apparatus, semiconductor device and method of manufacture are presented, wherein a hard mask layer and one or more etch stop layers are etched in an etching chamber. In an embodiment the semiconductor device is placed on a mounting platform at a first height and an etch process is performed, then the semiconductor device is moved to a second height within the chamber and a second etch process is performed, with the rotational speed of the semiconductor device reduced during movements in order to reduce the chance of cross contamination.Type: GrantFiled: October 18, 2019Date of Patent: April 20, 2021Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Wan Hsuan Hsu, Jao Sheng Huang, Yen-Chiu Kuo, Yu-Li Cheng, Ya Tzu Chen, Neng-Jye Yang, Chun-Li Chou
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Publication number: 20200402859Abstract: An apparatus includes a first source and a common drain and on opposite sides of a first gate surrounded by a first gate spacer, a second source and the common drain on opposite sides of a second gate surrounded by a second gate spacer, a first protection layer formed along a sidewall of the first gate spacer, wherein a top surface of the first protection layer has a first slope, a second protection layer formed along a sidewall of the second gate spacer, wherein a top surface of the second protection layer has a second slope, a lower drain contact between the first gate and the second gate and an upper drain contact over the lower drain contact and between the first gate and the second gate, wherein at least a portion of the upper drain contact is in contact with the first slope and the second slope.Type: ApplicationFiled: September 3, 2020Publication date: December 24, 2020Inventors: Wan Hsuan Hsu, I-Hsiu Wang, Yean-Zhaw Chen, Cheng-Wei Chang, Yu Shih Wang, Hsin-Yan Lu, Yi-Wei Chiu
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Patent number: 10770356Abstract: An apparatus includes a first source and a common drain and on opposite sides of a first gate surrounded by a first gate spacer, a second source and the common drain on opposite sides of a second gate surrounded by a second gate spacer, a first protection layer formed along a sidewall of the first gate spacer, wherein a top surface of the first protection layer has a first slope, a second protection layer formed along a sidewall of the second gate spacer, wherein a top surface of the second protection layer has a second slope, a lower drain contact between the first gate and the second gate and an upper drain contact over the lower drain contact and between the first gate and the second gate, wherein at least a portion of the upper drain contact is in contact with the first slope and the second slope.Type: GrantFiled: June 25, 2018Date of Patent: September 8, 2020Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Wan Hsuan Hsu, I-Hsiu Wang, Yean-Zhaw Chen, Cheng-Wei Chang, Yu Shih Wang, Hsin-Yan Lu, Yi-Wei Chiu
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Publication number: 20200266065Abstract: A middle layer removal method is provided. The method includes providing a substrate having a structure formed on the substrate, and forming a spacer layer on the structure. The method includes forming a mask layer over the spacer layer, the mask layer including a first layer, a second layer over the first layer, and a third layer over the second layer. The method also includes patterning the third layer of the mask layer, and etching the first layer and the second layer of the mask layer to form an opening to expose a bottom surface of the second layer. The method further includes removing the second layer using a wet etchant.Type: ApplicationFiled: May 8, 2020Publication date: August 20, 2020Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Nai-Chia CHEN, Wan Hsuan HSU, Chia-Wei WU, Neng-Jye YANG, Chun-Li CHOU
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Patent number: 10658179Abstract: Aspects of the disclosure provide a method. The method includes providing a substrate having a structure formed on the substrate, and forming a spacer layer on the structure. Then, the method includes forming a mask layer over the spacer layer. The mask layer includes a first layer, a second layer over the first layer, and a third layer over the second layer. Further, the method includes patterning the third layer of the mask layer, and etching the first layer and the second layer of the mask layer with a dry etching process using the third layer as an etch mask to form an opening that exposes a portion of the spacer layer. Then, the method includes removing the second layer using a wet etchant before a formation of a backfill material layer in the opening and over the first layer.Type: GrantFiled: August 17, 2018Date of Patent: May 19, 2020Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Nai-Chia Chen, Wan Hsuan Hsu, Chia-Wei Wu, Neng-Jye Yang, Chun-Li Chou
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Publication number: 20200058502Abstract: Aspects of the disclosure provide a method. The method includes providing a substrate having a structure formed on the substrate, and forming a spacer layer on the structure. Then, the method includes forming a mask layer over the spacer layer. The mask layer includes a first layer, a second layer over the first layer, and a third layer over the second layer. Further, the method includes patterning the third layer of the mask layer, and etching the first layer and the second layer of the mask layer with a dry etching process using the third layer as an etch mask to form an opening that exposes a portion of the spacer layer. Then, the method includes removing the second layer using a wet etchant before a formation of a backfill material layer in the opening and over the first layer.Type: ApplicationFiled: August 17, 2018Publication date: February 20, 2020Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Nai-Chia Chen, Wan Hsuan Hsu, Chia-Wei Wu, Neng-Jye Yang, Chun-Li Chou
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Publication number: 20180308761Abstract: An apparatus includes a first source and a common drain and on opposite sides of a first gate surrounded by a first gate spacer, a second source and the common drain on opposite sides of a second gate surrounded by a second gate spacer, a first protection layer formed along a sidewall of the first gate spacer, wherein a top surface of the first protection layer has a first slope, a second protection layer formed along a sidewall of the second gate spacer, wherein a top surface of the second protection layer has a second slope, a lower drain contact between the first gate and the second gate and an upper drain contact over the lower drain contact and between the first gate and the second gate, wherein at least a portion of the upper drain contact is in contact with the first slope and the second slope.Type: ApplicationFiled: June 25, 2018Publication date: October 25, 2018Inventors: Wan Hsuan Hsu, I-Hsiu Wang, Yean-Zhaw Chen, Cheng-Wei Chang, Yu Shih Wang, Hsin-Yan Lu, Yi-wei Chiu
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Patent number: 10037918Abstract: A method includes forming a first transistor and a second transistor over a substrate, wherein the first transistor and the second transistor share a drain/source region formed between a first gate of the first transistor and a second gate of the second transistor, forming a first opening in an interlayer dielectric layer and between the first gate and the second gate, depositing an etch stop layer in the first opening and on a top surface of the interlayer dielectric layer, depositing a dielectric layer over the etch stop layer, applying a first etching process to the dielectric layer until the etch stop layer is exposed, performing a second etching process on the etch stop layer until an exposed portion of the etch stop layer and portions of the dielectric layer have been removed.Type: GrantFiled: November 29, 2016Date of Patent: July 31, 2018Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Wan Hsuan Hsu, I-Hsiu Wang, Yean-Zhaw Chen, Cheng-Wei Chang, Yu Shih Wang, Hsin-Yan Lu, Yi-Wei Chiu
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Publication number: 20180151560Abstract: A method includes forming a first transistor and a second transistor over a substrate, wherein the first transistor and the second transistor share a drain/source region formed between a first gate of the first transistor and a second gate of the second transistor, forming a first opening in an interlayer dielectric layer and between the first gate and the second gate, depositing an etch stop layer in the first opening and on a top surface of the interlayer dielectric layer, depositing a dielectric layer over the etch stop layer, applying a first etching process to the dielectric layer until the etch stop layer is exposed, performing a second etching process on the etch stop layer until an exposed portion of the etch stop layer and portions of the dielectric layer have been removed.Type: ApplicationFiled: November 29, 2016Publication date: May 31, 2018Inventors: Wan Hsuan Hsu, I-Hsiu Wang, Yean-Zhaw Chen, Cheng-Wei Chang, Yu Shih Wang, Hsin-Yan Lu, Yi-Wei Chiu