Abstract: A structure includes first and second active areas, first and second gates and a data line. The first gate is continuous and crosses over the first active area and the second active area. The first gate corresponds to gate terminals of first and second transistors, and first source/drain regions of the first and the second active areas correspond to first source/drain terminals of the first and second transistors. The second gate includes first and second gate portions electrically isolated from each other. The first and second gate portions correspond to gate terminals of third and fourth transistors, respectively. The first gate portion crosses over the first active area, and the second gate portion crosses over the second active area. The first data line is coupled to the first source/drain regions of the first active area and the second active area.

Abstract: A semiconductor device includes first and second active areas, a first gate, a first conductive segment, a first via and a first continuous gate. The first and second active areas extend in a first direction. The first gate crosses over the first active area and the second active area. The first gate includes a first gate portion and a second gate portion electrically isolated from each other. The first conductive segment crosses over the first active area and the second active area. The first via is arranged above the first conductive segment. The first active area and the second active area are coupled through the first conductive segment to the first via. The first continuous gate is disposed between the first conductive segment and the first gate, and crossing over the first active area and the second active area.

Abstract: A structure includes first and second active areas, first and second gates and a data line. The first gate is continuous and crosses over the first active area and the second active area. The first gate corresponds to gate terminals of first and second transistors, and first source/drain regions of the first and the second active areas correspond to first source/drain terminals of the first and second transistors. The second gate includes first and second gate portions electrically isolated from each other. The first and second gate portions correspond to gate terminals of third and fourth transistors, respectively. The first gate portion crosses over the first active area, and the second gate portion crosses over the second active area. The first data line is coupled to the first source/drain regions of the first active area and the second active area.

Abstract: A semiconductor device includes first and second active areas, a first gate, a first conductive segment, a first via and a first continuous gate. The first and second active areas extend in a first direction. The first gate crosses over the first active area and the second active area. The first gate includes a first gate portion and a second gate portion electrically isolated from each other. The first conductive segment crosses over the first active area and the second active area. The first via is arranged above the first conductive segment. The first active area and the second active area are coupled through the first conductive segment to the first via. The first continuous gate is disposed between the first conductive segment and the first gate, and crossing over the first active area and the second active area.

Abstract: A structure includes first and second active areas, first and second gates and a data line. The first gate is continuous and crosses over the first active area and the second active area. The first gate corresponds to gate terminals of first and second transistors, and first source/drain regions of the first and the second active areas correspond to first source/drain terminals of the first and second transistors. The second gate includes first and second gate portions electrically isolated from each other. The first and second gate portions correspond to gate terminals of third and fourth transistors, respectively. The first gate portion crosses over the first active area, and the second gate portion crosses over the second active area. The first data line is coupled to the first source/drain regions of the first active area and the second active area.

Abstract: A structure includes a first data line and a first anti-fuse cell including first/second programming devices and first/second reading devices. The first programming device includes a first gate and first/second source/drain regions disposing on opposite sides of first gate. The second programming device includes a second gate separate from the first gate and coupled to a first word line and third/fourth source/drain regions disposing on opposite sides of second gate. The first reading device includes a third gate and fifth/sixth source/drain regions disposing on opposite sides of third gate. The second reading device includes a fourth gate and seventh/eighth source/drain regions disposing on opposite sides of fourth gate. The third/fourth gates are parts of the first continuous gate coupled to a second word line. The fifth/seventh source/drain regions are coupled to the second/fourth source/drain regions, respectively. The sixth/eighth source/drain regions are coupled to the first data line.

Abstract: A structure includes a first data line and a first anti-fuse cell including first/second programming devices and first/second reading devices. The first programming device includes a first gate and first/second source/drain regions disposing on opposite sides of first gate. The second programming device includes a second gate separate from the first gate and coupled to a first word line and third/fourth source/drain regions disposing on opposite sides of second gate. The first reading device includes a third gate and fifth/sixth source/drain regions disposing on opposite sides of third gate. The second reading device includes a fourth gate and seventh/eighth source/drain regions disposing on opposite sides of fourth gate. The third/fourth gates are parts of the first continuous gate coupled to a second word line. The fifth/seventh source/drain regions are coupled to the second/fourth source/drain regions, respectively. The sixth/eighth source/drain regions are coupled to the first data line.

Abstract: A programmable power discharge circuit and a method of discharging power are provided. The programmable power discharge circuit includes a programmable voltage controller, a detect circuit, and a discharge circuit. The programmable voltage controller selects and provides a threshold voltage by a voltage divider including a plurality of impedance components. The detect circuit detects a difference between the threshold voltage and a working voltage to decide whether the working voltage is discharged.

Abstract: A programmable power discharge circuit and a method of discharging power are provided. The programmable power discharge circuit includes a programmable voltage controller, a detect circuit, and a discharge circuit. The programmable voltage controller selects and provides a threshold voltage by a voltage divider including a plurality of impedance components. The detect circuit detects a difference between the threshold voltage and a working voltage to decide whether the working voltage is discharged.