Abstract: An electronic device includes a first substrate, a second substrate, a circuit layer, a diode element, and a conductive wire. The first substrate has a first surface, a second surface opposite to the first surface, and a first side surface connected between the first surface and the second surface. The second substrate has a third surface, a fourth surface opposite to the third surface, and a second side surface connected between the third surface and the fourth surface, wherein the fourth surface is disposed away from the first surface. The circuit layer and the diode element are disposed on the first surface. The diode element and the conductive wire are electrically connected to the circuit layer. A first portion of the conductive wire is disposed on the first side surface, and a second portion of the conductive wire is disposed on the second side surface.

Abstract: A semiconductor device includes an isolation structure in a substrate. The semiconductor device further includes a gate structure over a first region of the substrate, wherein the isolation structure surrounds the first region, the gate structure comprising a first section and a second section. The semiconductor device further includes a conductive field plate over the substrate, the conductive field plate extending between the first section and the second section and overlapping an edge of the first region, wherein the conductive field plate comprises a dielectric layer having a variable thickness. The semiconductor device further includes a first well in the substrate, wherein the first well overlaps the edge of the first region, and the first well extends underneath the isolation structure, and the conductive field plate extends beyond an outer-most edge of the first well.

Abstract: A semiconductor device includes an isolation structure in a substrate; and a gate structure over an active region of the substrate. The isolation structure surrounds the active region. The gate structure includes a first section parallel to a second section. The semiconductor device further includes a conductive field plate extending between the first section and the second section and overlapping an edge of the active region. A portion of the conductive field plate extends beyond the edge of the active region, The conductive field plate includes a dielectric layer having a first portion and a second portion, and the first portion is thicker than the second portion. The semiconductor device includes a first well overlapping the edge of the active region. The first well extends underneath the isolation structure. The conductive field plate extends beyond an outer-most edge of the first well.

Abstract: A device includes a first buried layer over a substrate, a second buried layer over the first buried layer, a first well over the first buried layer and the second buried layer, a first high voltage well, a second high voltage well and a third high voltage well extending through the first well, wherein the second high voltage well is between the first high voltage well and the third high voltage well, a first drain/source region in the first high voltage well, a first gate electrode over the first well, a second drain/source region in the second high voltage well and a first isolation region in the second high voltage well, and between the second drain/source region and the first gate electrode, wherein a bottom of the first isolation region is lower than a bottom of the second drain/source region.

Abstract: A device includes a first buried layer over a substrate, a second buried layer over the first buried layer, a first well over the first buried layer and the second buried layer, a first high voltage well, a second high voltage well and a third high voltage well extending through the first well, wherein the second high voltage well is between the first high voltage well and the third high voltage well, a first drain/source region in the first high voltage well, a first gate electrode over the first well, a second drain/source region in the second high voltage well and a first isolation region in the second high voltage well, and between the second drain/source region and the first gate electrode, wherein a bottom of the first isolation region is lower than a bottom of the second drain/source region.

Abstract: A semiconductor device includes an isolation structure in a substrate; and a gate structure over an active region of the substrate. The isolation structure surrounds the active region. The gate structure includes a first section parallel to a second section. The semiconductor device further includes a conductive field plate extending between the first section and the second section and overlapping an edge of the active region. A portion of the conductive field plate extends beyond the edge of the active region, The conductive field plate includes a dielectric layer having a first portion and a second portion, and the first portion is thicker than the second portion. The semiconductor device includes a first well overlapping the edge of the active region. The first well extends underneath the isolation structure. The conductive field plate extends beyond an outer-most edge of the first well.

Abstract: A method of manufacturing a semiconductor device includes forming a gate structure over an active region of a substrate, the gate structure comprising a first section and a second section. The first section and the second section dividing the active region into a first source/drain region between the first section and the second section, and a pair of second source/drain regions arranged on opposite sides of the gate structure. The method further includes forming a conductive field plate over the substrate, the field plate extending between the first section and the second section and overlapping an edge of the active region. The method further includes implanting a first well in the substrate, wherein the first well overlaps the edge of the active region. The method further includes forming an isolation structure in the substrate, wherein the conductive field plate extends over the isolation structure.

Abstract: A device includes a first buried layer over a substrate, a second buried layer over the first buried layer, a first well over the first buried layer and the second buried layer, a first high voltage well, a second high voltage well and a third high voltage well extending through the first well, wherein the second high voltage well is between the first high voltage well and the third high voltage well, a first drain/source region in the first high voltage well, a first gate electrode over the first well, a second drain/source region in the second high voltage well and a first isolation region in the second high voltage well, and between the second drain/source region and the first gate electrode, wherein a bottom of the first isolation region is lower than a bottom of the second drain/source region.

Abstract: A device includes a first buried layer over a substrate, a second buried layer over the first buried layer, a first well over the first buried layer and the second buried layer, a first high voltage well, a second high voltage well and a third high voltage well extending through the first well, wherein the second high voltage well is between the first high voltage well and the third high voltage well, a first drain/source region in the first high voltage well, a first gate electrode over the first well, a second drain/source region in the second high voltage well and a first isolation region in the second high voltage well, and between the second drain/source region and the first gate electrode, wherein a bottom of the first isolation region is lower than a bottom of the second drain/source region.

Abstract: A method of manufacturing a semiconductor device includes forming a gate structure over an active region of a substrate, the gate structure comprising a first section and a second section. The first section and the second section dividing the active region into a first source/drain region between the first section and the second section, and a pair of second source/drain regions arranged on opposite sides of the gate structure. The method further includes forming a conductive field plate over the substrate, the field plate extending between the first section and the second section and overlapping an edge of the active region. The method further includes implanting a first well in the substrate, wherein the first well overlaps the edge of the active region. The method further includes forming an isolation structure in the substrate, wherein the conductive field plate extends over the isolation structure.

Abstract: A semiconductor device includes a substrate having an active region, a drain region in the active region, a source region in the active region, a gate structure, and a conductive field plate. The gate structure extends in a first direction over the active region. The gate structure is arranged between the drain region and the source region in a second direction transverse to the first direction. The conductive field plate extends in the second direction over an edge of the active region.

Abstract: A device includes a first buried layer over a substrate, a second buried layer over the first buried layer, a first well over the first buried layer and the second buried layer, a first high voltage well, a second high voltage well and a third high voltage well extending through the first well, wherein the second high voltage well is between the first high voltage well and the third high voltage well, a first drain/source region in the first high voltage well, a first gate electrode over the first well, a second drain/source region in the second high voltage well and a first isolation region in the second high voltage well, and between the second drain/source region and the first gate electrode, wherein a bottom of the first isolation region is lower than a bottom of the second drain/source region.

Abstract: A device comprises a buried layer over a substrate, a first well over the buried layer, a first high voltage region and a second high voltage region extending through the first well, a first drain/source region in the first high voltage region, a first gate electrode over the first well, a first spacer on a first side of the first gate electrode, wherein the first spacer is between the first drain/source region and the first gate electrode, a second spacer on a second side of the first gate electrode, a second drain/source region in the second high voltage region and a first isolation region in the second high voltage region and between the second drain/source region and the first gate electrode.

Abstract: A device comprises a buried layer over a substrate, a first well over the buried layer, a first high voltage region and a second high voltage region extending through the first well, a first drain/source region in the first high voltage region, a first gate electrode over the first well, a first spacer on a first side of the first gate electrode, wherein the first spacer is between the first drain/source region and the first gate electrode, a second spacer on a second side of the first gate electrode, a second drain/source region in the second high voltage region and a first isolation region in the second high voltage region and between the second drain/source region and the first gate electrode.

Abstract: A high voltage transistor structure comprises a first double diffused region and a second double diffused region formed in a first well of a substrate, wherein the first and second double diffused regions are of the same conductivity as the substrate, a first drain/source region formed in the first double diffused region, a first gate electrode formed over the first well and a second drain/source region formed in the second double diffused region. The high voltage transistor structure further comprises a first spacer formed on a first side of the first gate electrode, wherein the first spacer is between the first drain/source region and the first gate electrode, a second spacer formed on a second side of the first gate electrode and a first oxide protection layer formed between the second drain/source region and the second spacer.

Abstract: A semiconductor structure includes a gate structure disposed on a substrate. At least one lightly doped region adjoins the gate structure in the substrate. The at least one lightly doped region has a first conductivity type. A source feature and a drain feature are on opposite sides of the gate structure in the substrate. The source feature and the drain feature have the first conductivity type. The source feature is in the at least one lightly doped region. A bulk pick-up region adjoins the source feature in the at least one lightly doped region. The bulk pick-up region has a second conductivity type.

Abstract: A semiconductor device includes a substrate having an active region, a drain region in the active region, a source region in the active region, a gate structure, and a conductive field plate. The gate structure extends in a first direction over the active region. The gate structure is arranged between the drain region and the source region in a second direction transverse to the first direction. The conductive field plate extends in the second direction over an edge of the active region.

Abstract: The present disclosure relates to a method of ultra-high voltage UHV device formation which utilizes a composite step oxide as a gate oxide to achieve isolation of the gate and drain-side spacer from the drain region. The thickness of the step gate oxide improves device breakdown voltage, and allows for the drain to be self-aligned to the gate, thus reducing device drift region and improves device on state resistance. The composite isolation layer comprises two or more dielectric layers which are formed through a series of deposition and etch steps including thermal oxidation and chemical vapor deposition. The composite isolation layer may then be etched to form a self-align structure which utilizes the spacers as hard mask to achieve a reduced device pitch relative to some prior art methods. A thicker gate oxide under one or both spacers can improve yield and high temperature operating life of the UHV device.

Abstract: A semiconductor structure includes a gate structure disposed on a substrate. At least one lightly doped region adjoins the gate structure in the substrate. The at least one lightly doped region has a first conductivity type. A source feature and a drain feature are on opposite sides of the gate structure in the substrate. The source feature and the drain feature have the first conductivity type. The source feature is in the at least one lightly doped region. A buck pick-up region adjoins the source feature in the at least one lightly doped region. The buck pick-up region has a second conductivity type.

Abstract: A semiconductor structure includes a semiconductor substrate; a first well region of a first conductivity type in the semiconductor substrate; a metal-containing layer on the first well region, wherein the metal-containing layer and the first well region form a Schottky barrier; and a first heavily doped region of the first conductivity type in the first well region, wherein the first heavily doped region is horizontally spaced apart from the metal-containing layer.