Patents by Inventor Wan Je Sung
Wan Je Sung has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 11688465Abstract: A memory system includes: a memory block including a plurality of pages each comprising a plurality of memory cells connected to bit lines and a word line of word lines, an address manager configured to output addresses corresponding to the plurality of pages, and a system data manager configured to generate index data corresponding to the each of the addresses, the index data indicating whether user data is inverted, and output the index data and information on a memory cell in which the index data is to be stored, respectively. The system data manager is configured to, determine memory cells connected to different bit lines from among memory cells included in adjacent pages corresponding to consecutive addresses of the addresses, as memory cells in which index data corresponding to the consecutive addresses are to be stored.Type: GrantFiled: June 28, 2021Date of Patent: June 27, 2023Assignee: SK hynix Inc.Inventors: Ie Ryung Park, Wan Je Sung, Dong Sop Lee, Bo Seok Jeong
-
Error correction decoder, error correction circuit having the same, and method of operating the same
Patent number: 11515898Abstract: Provided herein may be an error correction decoder, an error correction circuit having the error correction decoder, and a method of operating the error correction decoder. The error correction decoder may include a calculator configured to output an error correction message by performing an iterative decoding operation on a first codeword, a syndrome generator configured to generate a syndrome by calculating the error correction message and a parity check matrix and to output a number of iterations representing the number of times the iterative decoding operation has been performed, and an unsatisfied check node (UCN) value representing the number of unsatisfied check nodes in the syndrome, and a speed selector configured to output a speed code for controlling a speed of the iterative decoding operation depending on the number of iterations and the UCN value.Type: GrantFiled: October 9, 2020Date of Patent: November 29, 2022Assignee: SK hynix Inc.Inventors: Myung Jin Jo, Soon Young Kang, Wan Je Sung, Bo Seok Jeong -
Publication number: 20220208272Abstract: A memory system includes: a memory block including a plurality of pages each comprising a plurality of memory cells connected to bit lines and a word line of word lines, an address manager configured to output addresses corresponding to the plurality of pages, and a system data manager configured to generate index data corresponding to the each of the addresses, the index data indicating whether user data is inverted, and output the index data and information on a memory cell in which the index data is to be stored, respectively. The system data manager is configured to, determine memory cells connected to different bit lines from among memory cells included in adjacent pages corresponding to consecutive addresses of the addresses, as memory cells in which index data corresponding to the consecutive addresses are to be stored.Type: ApplicationFiled: June 28, 2021Publication date: June 30, 2022Inventors: Ie Ryung PARK, Wan Je SUNG, Dong Sop LEE, Bo Seok JEONG
-
Publication number: 20210359710Abstract: Provided herein may be an error correction decoder, an error correction circuit having the error correction decoder, and a method of operating the error correction decoder. The error correction decoder may include a calculator configured to output an error correction message by performing an iterative decoding operation on a first codeword, a syndrome generator configured to generate a syndrome by calculating the error correction message and a parity check matrix and to output a number of iterations representing the number of times the iterative decoding operation has been performed, and an unsatisfied check node (UCN) value representing the number of unsatisfied check nodes in the syndrome, and a speed selector configured to output a speed code for controlling a speed of the iterative decoding operation depending on the number of iterations and the UCN value.Type: ApplicationFiled: October 9, 2020Publication date: November 18, 2021Inventors: Myung Jin JO, Soon Young KANG, Wan Je SUNG, Bo Seok JEONG
-
Patent number: 11128315Abstract: Devices and methods for error correction are described. An exemplary error correction decoder includes a mapper configured to generate, based on a first set of read values corresponding to a first codeword, a first set of log likelihood ratio (LLR) values; a first buffer, coupled to the mapper, configured to store the first set of LLR values received from the mapper; and a node processor, coupled to the first buffer, configured to perform a first error correction decoding operation using the first set of LLR values received from the first buffer, wherein a first iteration of the first error correction decoding operation comprises refraining from updating values of one or more variable nodes, and performing a syndrome check using a parity check matrix and sign bits of the first set of LLR values stored in the first buffer.Type: GrantFiled: October 8, 2019Date of Patent: September 21, 2021Assignee: SK hynix Inc.Inventors: Myung Jin Jo, Dae Sung Kim, Wan Je Sung
-
Patent number: 11055164Abstract: There are provided an error correction decoder and a memory system having the same. The error correction decoder includes a node processor for performing at least one iteration of an error correction decoding based on at least one parameter used for an iterative decoding, a reliability information generator for generating reliability information corresponding to a current iteration upon a determination that the error correction decoding corresponding to the current iteration has been unsuccessful, and a parameter adjuster for adjusting the at least one parameter upon a determination that the reliability information satisfies a predetermined condition, and controlling the node processor to perform a next iteration based on the adjusted.Type: GrantFiled: November 6, 2019Date of Patent: July 6, 2021Assignee: SK hynix Inc.Inventors: Soon Young Kang, Dae Sung Kim, Wan Je Sung, Myung Jin Jo, Jae Young Han
-
Publication number: 20200341829Abstract: There are provided an error correction decoder and a memory system having the same. The error correction decoder includes a node processor for performing at least one iteration of an error correction decoding based on at least one parameter used for an iterative decoding, a reliability information generator for generating reliability information corresponding to a current iteration upon a determination that the error correction decoding corresponding to the current iteration has been unsuccessful, and a parameter adjuster for adjusting the at least one parameter upon a determination that the reliability information satisfies a predetermined condition, and controlling the node processor to perform a next iteration based on the adjusted.Type: ApplicationFiled: November 6, 2019Publication date: October 29, 2020Inventors: Soon Young Kang, Dae Sung Kim, Wan Je Sung, Myung Jin Jo, Jae Young Han
-
Publication number: 20200313693Abstract: Devices and methods for error correction are described. An exemplary error correction decoder includes a mapper configured to generate, based on a first set of read values corresponding to a first codeword, a first set of log likelihood ratio (LLR) values; a first buffer, coupled to the mapper, configured to store the first set of LLR values received from the mapper; and a node processor, coupled to the first buffer, configured to perform a first error correction decoding operation using the first set of LLR values received from the first buffer, wherein a first iteration of the first error correction decoding operation comprises refraining from updating values of one or more variable nodes, and performing a syndrome check using a parity check matrix and sign bits of the first set of LLR values stored in the first buffer.Type: ApplicationFiled: October 8, 2019Publication date: October 1, 2020Inventors: Myung Jin Jo, Dae Sung Kim, Wan Je Sung
-
Publication number: 20200067538Abstract: An error correction device includes: a plurality of variable node units each configured to: receive a hard decision bit and a channel reliability value having a first bit-precision; and perform an iteration of a decoding operation on the hard decision bit based on the channel reliability value; a plurality of check node units each configured to: receive one or more reference reliability values having a second bit-precision from one or more variable node units coupled thereto among the plurality of variable node units during the iteration; and transmit, based on the one or more reference reliability values, one or more check reliability values having the second bit-precision to the one or more variable node units coupled thereto, wherein, during the iteration, each of the plurality of variable node units further: receives one or more first check reliability values from one or more check node units coupled thereto among the plurality of check node units; and updates the hard decision bit with reference to the cType: ApplicationFiled: December 17, 2018Publication date: February 27, 2020Inventors: Dae Sung KIM, Myung Jin JO, Soon Young KANG, Wan Je SUNG
-
Patent number: 10554228Abstract: An error correction device includes: a plurality of variable node units each configured to: receive a hard decision bit and a channel reliability value having a first bit-precision; and perform an iteration of a decoding operation on the hard decision bit based on the channel reliability value; a plurality of check node units each configured to: receive one or more reference reliability values having a second bit-precision from one or more variable node units coupled thereto among the plurality of variable node units during the iteration; and transmit, based on the one or more reference reliability values, one or more check reliability values having the second bit-precision to the one or more variable node units coupled thereto, wherein, during the iteration, each of the plurality of variable node units further: receives one or more first check reliability values from one or more check node units coupled thereto among the plurality of check node units; and updates the hard decision bit with reference to the cType: GrantFiled: December 17, 2018Date of Patent: February 4, 2020Assignee: SK hynix Inc.Inventors: Dae Sung Kim, Myung Jin Jo, Soon Young Kang, Wan Je Sung