Abstract: A memory system may improve the endurance and performance of a plurality of memories included in the memory system mounted on a server system or a data processing system. For example, the memory system may throttle energy of a first memory using a second memory having a different characteristic from the first memory, control accesses to a memory region according to a refresh cycle, and control accesses to memories having different temperatures according to a priority of a request for each of the memories.

Abstract: A memory system may improve the endurance and performance of a plurality of memories included in the memory system mounted on a server system or a data processing system. For example, the memory system may throttle energy of a first memory using a second memory having a different characteristic from the first memory, control accesses to a memory region according to a refresh cycle, and control accesses to memories having different temperatures according to a priority of a request for each of the memories.

Abstract: A converged memory device includes: a first memory group having first characteristics; a second memory group having second characteristics that are different from the first characteristics; and a controller configured to migrate predetermined data of the second memory group into a cache region in the first memory group, wherein the controller is further configured to migrate data of the second memory group into the cache region by using the cache region as a buffer when an energy throttling operation is performed on the second memory group.

Abstract: In accordance with an embodiment of the present disclosure, an image synchronization device includes a light emitting source configured to emit light at intervals of a predetermined time, a sampling phase calibration circuit configured to calibrate a sampling phase of each of the first image sensor and the second image sensor on the basis of a light emitting timing of the light emitting source and a delay calibration circuit configured to generate delay information on the basis of a result of comparison between first image information transmitted from the first image sensor and second image information transmitted from the second image sensor.

Abstract: In accordance with an embodiment of the present disclosure, an image synchronization device includes a light emitting source configured to emit light at intervals of a predetermined time, a sampling phase calibration circuit configured to calibrate a sampling phase of each of the first image sensor and the second image sensor on the basis of a light emitting timing of the light emitting source and a delay calibration circuit configured to generate delay information on the basis of a result of comparison between first image information transmitted from the first image sensor and second image information transmitted from the second image sensor.

Abstract: A converged memory device includes: a first memory group having first characteristics; a second memory group having second characteristics that are different from the first characteristics; and a controller configured to migrate predetermined data of the second memory group into a cache region in the first memory group, wherein the controller is further configured to migrate data of the second memory group into the cache region by using the cache region as a buffer when an energy throttling operation is performed on the second memory group.

Abstract: A converged memory device includes: a first memory group having first characteristics; a second memory group having second characteristics that are different from the first characteristics; and a controller configured to migrate predetermined data of the second memory group into a cache region in the first memory group, wherein the controller is further configured to migrate data of the second memory group into the cache region by using the cache region as a buffer when an energy throttling operation is performed on the second memory group.

Abstract: A convergence memory device includes a plurality of memories and a controller configured to control the plurality of memories. When an access request for accessing a storage region included in one or more of the memories is received, the controller determines whether the access request has been received a preset number of times or more within a refresh cycle. When the controller determines that the access request has been received the preset number of times or more, the controller postpones processing of the received access request.

Abstract: A memory system may improve the endurance and performance of a plurality of memories included in the memory system mounted on a server system or a data processing system. For example, the memory system may throttle energy of a first memory using a second memory having a different characteristic from the first memory, control accesses to a memory region according to a refresh cycle, and control accesses to memories having different temperatures according to a priority of a request for each of the memories.

Abstract: A convergence memory device includes a plurality of memories and a controller configured to control the plurality of memories. When an access request for accessing a storage region included in one or more of the memories is received, the controller determines whether the access request has been received a preset number of times or more within a refresh cycle. When the controller determines that the access request has been received the preset number of times or more, the controller postpones processing of the received access request.

Abstract: A converged memory device includes: a first memory group having first characteristics; a second memory group having second characteristics that are different from the first characteristics; and a controller configured to migrate predetermined data of the second memory group into a cache region in the first memory group, wherein the controller is further configured to migrate data of the second memory group into the cache region by using the cache region as a buffer when an energy throttling operation is performed on the second memory group.