Patents by Inventor Wan-Jun ROH

Wan-Jun ROH has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230094144
    Abstract: A memory system may improve the endurance and performance of a plurality of memories included in the memory system mounted on a server system or a data processing system. For example, the memory system may throttle energy of a first memory using a second memory having a different characteristic from the first memory, control accesses to a memory region according to a refresh cycle, and control accesses to memories having different temperatures according to a priority of a request for each of the memories.
    Type: Application
    Filed: November 30, 2022
    Publication date: March 30, 2023
    Inventors: Wan-Jun Roh, Hyun-Sup Kim, Hyung-Sik Won
  • Patent number: 11544168
    Abstract: A memory system may improve the endurance and performance of a plurality of memories included in the memory system mounted on a server system or a data processing system. For example, the memory system may throttle energy of a first memory using a second memory having a different characteristic from the first memory, control accesses to a memory region according to a refresh cycle, and control accesses to memories having different temperatures according to a priority of a request for each of the memories.
    Type: Grant
    Filed: April 24, 2020
    Date of Patent: January 3, 2023
    Assignee: SK hynix Inc.
    Inventors: Wan-Jun Roh, Hyung-Sup Kim, Hyung-Sik Won
  • Patent number: 11487661
    Abstract: A converged memory device includes: a first memory group having first characteristics; a second memory group having second characteristics that are different from the first characteristics; and a controller configured to migrate predetermined data of the second memory group into a cache region in the first memory group, wherein the controller is further configured to migrate data of the second memory group into the cache region by using the cache region as a buffer when an energy throttling operation is performed on the second memory group.
    Type: Grant
    Filed: September 15, 2020
    Date of Patent: November 1, 2022
    Assignee: SK hynix Inc.
    Inventor: Wan-Jun Roh
  • Patent number: 11016887
    Abstract: A converged memory device includes: a first memory group having first characteristics; a second memory group having second characteristics that are different from the first characteristics; and a controller configured to migrate predetermined data of the second memory group into a cache region in the first memory group, wherein the controller is further configured to migrate data of the second memory group into the cache region by using the cache region as a buffer when an energy throttling operation is performed on the second memory group.
    Type: Grant
    Filed: October 18, 2018
    Date of Patent: May 25, 2021
    Assignee: SK hynix Inc.
    Inventor: Wan-Jun Roh
  • Publication number: 20200409842
    Abstract: A converged memory device includes: a first memory group having first characteristics; a second memory group having second characteristics that are different from the first characteristics; and a controller configured to migrate predetermined data of the second memory group into a cache region in the first memory group, wherein the controller is further configured to migrate data of the second memory group into the cache region by using the cache region as a buffer when an energy throttling operation is performed on the second memory group.
    Type: Application
    Filed: September 15, 2020
    Publication date: December 31, 2020
    Inventor: Wan-Jun ROH
  • Patent number: 10795613
    Abstract: A convergence memory device includes a plurality of memories and a controller configured to control the plurality of memories. When an access request for accessing a storage region included in one or more of the memories is received, the controller determines whether the access request has been received a preset number of times or more within a refresh cycle. When the controller determines that the access request has been received the preset number of times or more, the controller postpones processing of the received access request.
    Type: Grant
    Filed: October 12, 2018
    Date of Patent: October 6, 2020
    Assignee: SK Hynix Inc.
    Inventor: Wan-Jun Roh
  • Publication number: 20200257604
    Abstract: A memory system may improve the endurance and performance of a plurality of memories included in the memory system mounted on a server system or a data processing system. For example, the memory system may throttle energy of a first memory using a second memory having a different characteristic from the first memory, control accesses to a memory region according to a refresh cycle, and control accesses to memories having different temperatures according to a priority of a request for each of the memories.
    Type: Application
    Filed: April 24, 2020
    Publication date: August 13, 2020
    Inventors: Wan-Jun ROH, Hyung-Sup KIM, Hyung-Sik WON
  • Publication number: 20190258426
    Abstract: A convergence memory device includes a plurality of memories and a controller configured to control the plurality of memories. When an access request for accessing a storage region included in one or more of the memories is received, the controller determines whether the access request has been received a preset number of times or more within a refresh cycle. When the controller determines that the access request has been received the preset number of times or more, the controller postpones processing of the received access request.
    Type: Application
    Filed: October 12, 2018
    Publication date: August 22, 2019
    Inventor: Wan-Jun ROH
  • Publication number: 20190129847
    Abstract: A converged memory device includes: a first memory group having first characteristics; a second memory group having second characteristics that are different from the first characteristics; and a controller configured to migrate predetermined data of the second memory group into a cache region in the first memory group, wherein the controller is further configured to migrate data of the second memory group into the cache region by using the cache region as a buffer when an energy throttling operation is performed on the second memory group.
    Type: Application
    Filed: October 18, 2018
    Publication date: May 2, 2019
    Inventor: Wan-Jun ROH