Abstract: A device includes first and second gate structures respectively extending across the first and second fins, and a gate isolation plug between a longitudinal end of the first gate structure and a longitudinal end of the second gate structure. The gate isolation plug comprises a first dielectric layer and a second dielectric layer over the first dielectric layer. The first dielectric layer has an upper portion and a lower portion below the upper portion. The upper portion has a thickness smaller than a thickness of the lower portion of the first dielectric layer.

Abstract: A carrier structure is provided, in which at least one positioning area is defined on a chip-placement area of a package substrate, and at least one alignment portion is disposed on the positioning area. Therefore, the precision of manufacturing the alignment portion is improved by disposing the positioning area on the chip-placement area, such that the carrier structure can provide a better alignment mechanism for the chip placement operation.

Abstract: An exposure device and method for semiconductor manufacturing, focusing on the creation of exposure patterns with High Dynamic Range (HDR) capabilities, is disclosed. The exposure device includes a laser source, a first spatial light modulator (SLM), specifically a Liquid Crystal on Silicon (LCOS) device, and a second SLM, specifically a Digital Micromirror Device (DMD). The LCOS is positioned upstream in the optical path and is optimized for modulating the phase of the laser. It also directs the laser light towards specific areas on the DMD, crucial for enhancing detail and contrast in exposure patterns. The DMD, placed downstream, is composed of micromirrors that modulate the amplitude of the reflected laser, essential for achieving HDR in exposure patterns. This cooperative interaction between the LCOS and DMD allows for the creation of exposure patterns with a wide range of light intensities, from very bright to very dark, thereby achieving high dynamic range.

Abstract: The present disclosure pertains to a photomask cleaning device suitable for cleaning a photomask. The interior of the photomask cleaning device is equipped with a cleaning area and a photomask flipping area. The photomask has a first surface and a second surface, with a pattern and a photomask protective film set on the first surface. The photomask protective film covers the pattern. The photomask cleaning device includes a photomask flipping mechanism, a transport mechanism, and at least one cleaning mechanism. The photomask flipping mechanism is located within the photomask flipping area and is configured to flip the photomask. Additionally, the transport mechanism is used to transport the photomask, enabling the photomask to move between the photomask flipping area and the cleaning area. The cleaning mechanism is located within the cleaning area and is used to clean the photomask.

Abstract: A polymer is formed by capping a copolymer-graft-polylactone with an alcohol, wherein the copolymer is copolymerized from an anhydride monomer with a double bond, a monomer with a double bond, and an initiator. The polymer can be mixed with an organic solvent and pigment powder to form a dispersion. The dispersion can be mixed with a binder to form a paint.

Abstract: An exemplary gate driving circuit is adapted for driving a display panel including multiple pixels and includes a first gate driving unit string and a second gate driving unit string. The first gate driving unit string includes multiple cascade-connected first gate driving units and receives a start pulse. The first gate driving units are for generating output pulses to drive the pixels. The second gate driving unit string includes multiple cascade-connected second gate driving units and receives the start pulse. The second gate driving units are for generating output pulses to drive the pixels. The output pulse generated from one of the second gate driving units is provided to one of first gate driving units to determine whether to disable the output pulse of the first gate driving unit which receives the output pulse generated from the second gate driving units.

Abstract: An exemplary gate driving circuit is adapted for driving a display panel including multiple pixels and includes a first gate driving unit string and a second gate driving unit string. The first gate driving unit string includes multiple cascade-connected first gate driving units and receives a start pulse. The first gate driving units are for generating output pulses to drive the pixels. The second gate driving unit string includes multiple cascade-connected second gate driving units and receives the start pulse. The second gate driving units are for generating output pulses to drive the pixels. The output pulse generated from one of the second gate driving units is provided to one of first gate driving units to determine whether to disable the output pulse of the first gate driving unit which receives the output pulse generated from the second gate driving units.

Abstract: An exemplary layout structure of a shift register circuit includes a first shift register and a second shift register arranged adjacent to the first shift register. The first shift register and the second shift register each receive a first signal and a second signal phase-inverted with respect to the first signal. Moreover, the first shift register and the second shift register share a common signal routing trace for receiving the first signal. The common signal routing trace is arranged extending into between the first shift register and the second shift register.

Abstract: A driving circuit unit outputting a driving signal includes an input unit, an assistant output unit and an output unit. The input unit is coupled to an input node and receives a start signal to make the input node have a potential. The assistant output unit receives a first clock signal to increase the potential of the input node. The output unit receives a second clock signal to increase the potential of the input node and outputs the driving signal. A gate driving circuit is also disclosed.

Abstract: A gate driving circuit for driving plural scan lines of a liquid crystal display includes N driving circuit units and a control unit. Each of the N driving circuit units sequentially outputs a driving signal to drive a corresponding scan line of the scan lines. The control unit outputs a positive-phase and an opposite-phase clock signal to control the N driving circuit units. After an Nth driving circuit unit of the N driving circuit units outputs the driving signal, the control unit transmits a control signal to at least one of the N driving circuit units. A method for driving the foregoing gate driving circuit is also disclosed.

Abstract: A shift register array is provided. The shift register array includes a plurality of shift registers connected in serial. The shift register includes a first transistor coupled between a first input terminal and a first node, a second transistor coupled between a first clock input terminal and an output terminal and a pull-up unit. The first transistor has a gate coupled to the first input terminal. The second transistor has a gate coupled to the first node. The pull-up unit includes a third transistor coupled between the first node and a ground, a capacitor coupled between the first clock input terminal and the second node and a fourth transistor coupled between the second node and the ground. The third transistor has a gate coupled to a second node. The fourth transistor has a gate coupled to the first node.

Abstract: A shift register array is provided. The shift register array includes a plurality of shift registers connected in serial. The shift register includes a first transistor coupled between a first input terminal and a first node, a second transistor coupled between a first clock input terminal and an output terminal and a pull-up unit. The first transistor has a gate coupled to the first input terminal. The second transistor has a gate coupled to the first node. The pull-up unit includes a third transistor coupled between the first node and a ground, a capacitor coupled between the first clock input terminal and the second node and a fourth transistor coupled between the second node and the ground. The third transistor has a gate coupled to a second node. The fourth transistor has a gate coupled to the first node.

Abstract: This invention discloses a fan-out wire structure for use in a display panel of a display device. The fan-out wire structure comprises a first metal layer, a first insulation layer, and a second metal layer. The first insulation layer is formed on the first metal layer and the second metal layer is formed on the first insulation layer, and the first metal layer and the second metal layer are electrically connected by a conductive material, so as to modulate the resistance of the fan-out wire structure by modulating the length of the second metal layer and the conductive material.

Abstract: A gate driving circuit for driving plural scan lines of a liquid crystal display includes N driving circuit units and a control unit. Each of the N driving circuit units sequentially outputs a driving signal to drive a corresponding scan line of the scan lines. The control unit outputs a positive-phase and an opposite-phase clock signal to control the N driving circuit units. After an Nth driving circuit unit of the N driving circuit units outputs the driving signal, the control unit transmits a control signal to at least one of the N driving circuit units. A method for driving the foregoing gate driving circuit is also disclosed.

Abstract: A driving circuit unit outputting a driving signal includes an input unit, an assistant output unit and an output unit. The input unit is coupled to an input node and receives a start signal to make the input node have a potential. The assistant output unit receives a first clock signal to increase the potential of the input node. The output unit receives a second clock signal to increase the potential of the input node and outputs the driving signal. A gate driving circuit is also disclosed.

Abstract: A display device is disclosed, which has a printed circuit board, a display panel, data driver chips and a scan driver circuit. The display panel has a substrate, scan lines and data lines. The scan lines are disposed on the substrate, and the data lines perpendicular to the scan lines are disposed on the substrate. The data driver chips, which are cascaded and mounted on the substrate, are electrically connected to the data lines and the printed circuit board. The scan driver circuit is formed on the substrate and electrically connected to the scan lines and the printed circuit board.

Abstract: This invention discloses a fan-out wire structure for use in a display panel of a display device. The fan-out wire structure comprises a first metal layer, a first insulation layer, and a second metal layer. The first insulation layer is formed on the first metal layer and the second metal layer is formed on the first insulation layer, and the first metal layer and the second metal layer are electrically connected by a conductive material, so as to modulate the resistance of the fan-out wire structure by modulating the length of the second metal layer and the conductive material.

Abstract: A display panel comprising a first substrate, a second substrate and a plurality of pillar spacers is provided. The first substrate comprises a first base and a black matrix layer with a plurality of openings. The black matrix layer is disposed on the lower surface of the first base. The second substrate is disposed below the first substrate and separated at a predetermined distance from the first substrate. The plurality of pillar spacers for maintaining the predetermined distance. Each of the pillar spacer having a first end and a second end. The first end is inserted into the portion of the plurality of openings, and the second end extends to contact with the second substrate.