Abstract: A high-voltage transistor may include a planar active region for a first source/drain active region, a second source/drain active region, and/or a channel active region. The planar active region(s) are included instead of a plurality of fin active regions to reduce the amount of surface area of the active regions in the high-voltage transistor that is in contact with surrounding dielectric layers of the high-voltage transistor. In other words, the planar active region(s) reduce the interface surface area between the silicon-based active regions of the high-voltage transistor and the surrounding oxide-based dielectric layers. The reduced interface surface area may reduce the occurrence of charge trapping in the high-voltage transistor, which may result in increased performance stability for the high-voltage transistor and/or may provide increased operational lifetime of the high-voltage transistor.

Abstract: Trench isolation connectors are disclosed herein for stacked semiconductor structures, and particularly, for stacked semiconductor structures having high voltage devices. An exemplary stacked device arrangement includes a first device substrate having a first device and a second device substrate having a second device. An isolation structure disposed in the second device substrate surrounds the second device. The isolation structure extends through the second device substrate from a first surface of the second device substrate to a second surface of the second device substrate. A conductive connector is disposed in the isolation structure. The conductive connector is connected to the second device and the first device. The conductive connector extends from the first surface of the second device substrate to the second surface of the second device substrate. The first device and the second device may be a first high voltage device and a second high voltage device, respectively.

Abstract: A semiconductor device includes: a first semiconductor region disposed over a second semiconductor region, wherein the first and second semiconductor regions have a first doping type and a second doping type, respectively; a first source/drain contact region and a second source/drain contact region having the second doping type and laterally spaced; and a gate electrode disposed laterally between the first and second source/drain contact regions, wherein the gate electrode comprises a first sidewall relatively closer to the first source/drain region and a second sidewall relatively closer to the second source/drain region, and wherein respective cross-sectional areas of the first and second sidewalls of the gate electrode are different from each other.

Abstract: A semiconductor device includes: a first semiconductor region disposed over a second semiconductor region, wherein the first and second semiconductor regions have a first doping type and a second doping type, respectively; a first source/drain contact region and a second source/drain contact region having the second doping type and laterally spaced; and a gate electrode disposed laterally between the first and second source/drain contact regions, wherein the gate electrode comprises a first sidewall relatively closer to the first source/drain region and a second sidewall relatively closer to the second source/drain region, and wherein respective cross-sectional areas of the first and second sidewalls of the gate electrode are different from each other.

Abstract: A semiconductor device includes: a first semiconductor region disposed over a second semiconductor region, wherein the first and second semiconductor regions have a first doping type and a second doping type, respectively; a first source/drain contact region and a second source/drain contact region having the second doping type and laterally spaced; and a gate electrode disposed laterally between the first and second source/drain contact regions, wherein the gate electrode comprises a first sidewall relatively closer to the first source/drain region and a second sidewall relatively closer to the second source/drain region, and wherein respective cross-sectional areas of the first and second sidewalls of the gate electrode are different from each other.

Abstract: A laterally diffused metal-oxide-semiconductor (LDMOS) transistor with a vertical channel region is provided. A first semiconductor region is formed over a second semiconductor region and with a first doping type. The second semiconductor region has a second doping type different than the first doping type. A gate electrode is formed laterally adjacent to the first semiconductor region and extending along a side boundary of the first semiconductor region. A first source/drain contact region and a second source/drain contact region are respectively formed on opposite sides of the gate electrode and with the second doping type. The first source/drain contact region is further formed over the first semiconductor region. A method for manufacturing the LDMOS transistor is also provided.