Abstract: Bus interface units interposed between a multiple processor bus and individually coupled to the respective processors in a complex incorporating a multitude of processors, where each bus interface unit includes block snoop control registers responsive to signals from a system memory controller including enhanced function supportive of I/O devices with and without block snooping compatibility. The BIU provides functionality for the bus of the multiple processors to be processor independent. This architecture reduces the number of snoop cycles which must access the processor bus, thereby effectively increasing the available processor bus bandwidth. This in turn effectively increases overall system performance.

Abstract: A mechanism is provided for supporting stack cache memory device management of POP read or PUSH write data in a computer system. The computer system further comprises a main memory and a processor associated with the stack cache memory device. The stack cache memory device includes at least one cache line having a plurality of address spaces arranged from a lowest address to a highest address. In response to the processor initiating a POP read or PUSH write operation, the mechanism provides logic for preventing placement of data in the cache which will not be reused by the processor, and for further preventing removal of data which may be reused by the processor.

Abstract: A method and system in a superscalar data processing system are disclosed for the temporary designation of a physical register as a particular general register. The data processing system is capable of processing multiple instructions during a single clock cycle. Physical registers are established. None of the physical registers are initially designated as a particular general register. No general registers exist which are initially designated as particular general registers. For each of the multiple instructions, a determination is made as to whether the instruction is a load register instruction. If the instruction is a load register instruction, a determination is made as to whether the instruction is associated with a logical register name. Each one of the logical register names identifies a different general register.

Abstract: A memory controller having request queue and snoop tables is provided for functioning with bus interface units interposed between a multiple processor bus and individually coupled to the respective processors in a complex incorporating a multitude of processors, where each bus interface unit includes block snoop control registers responsive to signals from a system memory controller including enhanced function supportive of I/O devices with and without block snooping compatibility. The tables are compared to minimize and more efficiently institute snoop operations as a function of the presence or absence of the same listings in the tables. The BIU provides functionality for the bus of the multiple processors to be processor independent. This architecture reduces the number of snoop cycles which must access the processor bus, thereby effectively increasing the available processor bus bandwidth. This in turn effectively increases overall system performance.

Abstract: Bus interface units interposed between a multiple processor bus and individually coupled to the respective processors in a complex incorporating a multitude of processors, where each bus interface unit includes block snoop control registers responsive to signals from a system memory controller including enhanced function supportive of I/O devices with and without block snooping compatibility. The BIU provides functionality for the bus of the multiple processors to be processor independent. This architecture reduces the number of snoop cycles which must access the processor bus, thereby effectively increasing the available processor bus bandwidth. This in turn effectively increases overall system performance.

Abstract: A stack cache memory mechanism and method for managing the mechanism are provided. The mechanism comprises a data array including a plurality of storage elements in which stack data may be stored, and a plurality of individual stack tag sets for identifying beginning and ending locations of a corresponding plurality of individual stacks contained within the data array. Each of the individual stack tag sets comprise (i) a first register for containing an address in the data array corresponding to the top of a stack associated with that individual stack tag set and (ii) a second register for containing an address in the data array corresponding to the bottom of a stack associated with that individual stack tag set. A backward pointer array comprises a plurality of backward pointers which map each of the plurality of stack tag sets to address locations in the data array.

Abstract: In a computer system having a central processing unit (CPU) in circuit communication with a memory via a memory bus and having first and second peripheral bus controllers generating first and second dissimilar peripheral buses, a multibus arbiter is provided for arbitrating access of a memory bus between the two dissimilar buses. The multibus arbiter has an assignment register, a time slot pointer, and an arbitration circuit. The length of the assignment register and time slot pointer controls the granularity of control of accesses to the memory bus by the peripheral buses. The assignment register holds a multibit assignment value that determines which of the two peripheral buses will be given access to the memory bus for a given time slot during contention.

Abstract: A local processor is connected to one port of a dual port memory controller. A bus having a BURST signal line is connected to the other port. The memory controller controls access to a local memory. A remote processor can perform a semaphore operation on a semaphore stored in the local memory by translating a LOCK signal from the remote processor into a bus BURST signal that is activated for a period allowing the remote processor to read and modify the semaphore. While the semaphore operation is being performed, the local processor can access the local memory.

Abstract: In a computer system, a plurality of input/output processors (IOP's) are connected via an asynchronous input/output bus, called an "SPD" bus, to one side of an input/output interface controller (IOIC). The other side of the IOIC is connected to a storage controller (SC) via a synchronous bus called an "adapter" bus. The SC is connected to a common system memory and possibly also to an instruction processing unit. The IOIC comprises at least one shared DMA facility for executing DMA read/write storage operations requested by the IOP's via the SPD bus. Each shared DMA facility includes a buffer for holding control information and data to be transmitted between the SC and one of the IOP's. This enables the SPD bus to be released for utilization by otehr IOP's connected thereto during periods of "storage latency" that occur after a DMA storage operation has been initiated by one IOP.

Abstract: A unique high-speed hardware arrangement for generating double-level address translations in combination a translation look-aside buffer (TLB) structure that can store and lookup intermediate translations during a double-level translation. The hardware proceeds to the completion of a double-level translation without having to backup its operation, although an intermediate TLB miss is encountered, without danger of CPU deadlock occurring. The hardware arrangement also performs all single-level address translations required by the system.