Patents by Inventor Wan Lay Looi

Wan Lay Looi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8134196
    Abstract: An integrated circuit system is provided including forming a substrate, forming a first contact having multiple conductive layers over the substrate and a layer of the multiple conductive layers on other layers of the multiple conductive layers, forming a dielectric layer on the first contact, and forming a second contact on the dielectric layer and over the first contact.
    Type: Grant
    Filed: September 1, 2006
    Date of Patent: March 13, 2012
    Assignee: STATS ChipPAC Ltd.
    Inventors: Yaojian Lin, Haijing Cao, Wan Lay Looi, Eng Seng Lim
  • Patent number: 8008770
    Abstract: An integrated circuit package system includes an integrated circuit, and forming a patterned redistribution pad over the integrated circuit.
    Type: Grant
    Filed: November 2, 2006
    Date of Patent: August 30, 2011
    Assignee: Stats Chippac Ltd.
    Inventors: Yaojian Lin, Romeo Emmanuel P. Alvarez, Haijing Cao, Wan Lay Looi
  • Patent number: 7443039
    Abstract: An integrated circuit package is provided with a substrate having first and second contact pads exposed through a passivation layer on the substrate. A first metallurgy layer is over the substrate. A second metallurgy layer is over the first metallurgy layer. A protective layer is over the first contact pad.
    Type: Grant
    Filed: December 23, 2005
    Date of Patent: October 28, 2008
    Assignee: ST Assembly Test Services Ltd.
    Inventors: Lun Zhao, Wan Lay Looi, Kyaw Oo Aung, Yonggang Jin, Jae-Yong Song, Won Sun Shin
  • Patent number: 7381634
    Abstract: An integrated circuit system provides a precursor for an integrated wire bond and flip chip structure. The precursor has a plurality of contact pads thereon. A layer of titanium is deposited on the precursor. A layer of nickel-vanadium is deposited on the layer of titanium. A layer of copper is deposited on the layer of nickel-vanadium. A mask is formed on at least a portion of the layer of copper. Portions of the layers of copper and nickel-vanadium not protected by the mask are removed to expose portions of the layer of titanium. The exposed portions of the layer of titanium are etched with an etching solution consisting of an etchant, a viscosity modifier, and an oxidizer.
    Type: Grant
    Filed: April 13, 2005
    Date of Patent: June 3, 2008
    Assignee: Stats Chippac Ltd.
    Inventors: Yaojian Lin, Byung Tai Do, Wan Lay Looi, Haijing Cao
  • Publication number: 20070114639
    Abstract: An integrated circuit package system includes an integrated circuit, and forming a patterned redistribution pad over the integrated circuit.
    Type: Application
    Filed: November 2, 2006
    Publication date: May 24, 2007
    Applicant: STATS ChipPAC Ltd.
    Inventors: Yaojian Lin, Romeo Alvarez, Haijing Cao, Wan Lay Looi
  • Publication number: 20070108615
    Abstract: An integrated circuit system is provided including forming a substrate, forming a first contact having multiple conductive layers over the substrate and a layer of the multiple conductive layers on other layers of the multiple conductive layers, forming a dielectric layer on the first contact, and forming a second contact on the dielectric layer and over the first contact.
    Type: Application
    Filed: September 1, 2006
    Publication date: May 17, 2007
    Applicant: STATS ChipPAC Ltd.
    Inventors: Yaojian Lin, Haijing Cao, Wan Lay Looi, Eng Seng Lim
  • Publication number: 20060231948
    Abstract: An integrated circuit system provides a precursor for an integrated wire bond and flip chip structure. The precursor has a plurality of contact pads thereon. A layer of titanium is deposited on the precursor. A layer of nickel-vanadium is deposited on the layer of titanium. A layer of copper is deposited on the layer of nickel-vanadium. A mask is formed on at least a portion of the layer of copper. Portions of the layers of copper and nickel-vanadium not protected by the mask are removed to expose portions of the layer of titanium. The exposed portions of the layer of titanium are etched with an etching solution consisting of an etchant, a viscosity modifier, and an oxidizer.
    Type: Application
    Filed: April 13, 2005
    Publication date: October 19, 2006
    Applicant: STATS CHIPPAC LTD.
    Inventors: Yaojian Lin, Byung Tai Do, Wan Lay Looi, Haijing Cao
  • Publication number: 20060197223
    Abstract: An integrated circuit package is provided with a substrate having first and second contact pads exposed through a passivation layer on the substrate. A first metallurgy layer is over the substrate. A second metallurgy layer is over the first metallurgy layer. A protective layer is over the first contact pad.
    Type: Application
    Filed: December 23, 2005
    Publication date: September 7, 2006
    Applicant: ST ASSEMBLY TEST SERVICES LTD.
    Inventors: Lun Zhao, Wan Lay Looi, Kyaw Oo Aung, Yonggang Jin, Jae-Yong Song, Won Sun Shin
  • Patent number: 7005370
    Abstract: A method for manufacturing an integrated circuit package is provided with a substrate having first and second contact pads exposed through a passivation layer on the substrate. A first metallurgy layer is formed over the substrate. A second metallurgy layer is formed over the first metallurgy layer. The first metallurgy layer is removed while leaving a portion thereof over the second contact pad. The second metallurgy layer is removed while leaving a portion thereof over the second contact pad. A protective layer is formed over the first contact pad while removing the first metallurgy layer.
    Type: Grant
    Filed: May 13, 2004
    Date of Patent: February 28, 2006
    Assignee: ST Assembly Test Services Ltd.
    Inventors: Lun Zhao, Wan Lay Looi, Kyaw Oo Aung, Yonggang Jin, Jae-Yong Song, Won Sun Shin