Patents by Inventor Wan-Lin Chen
Wan-Lin Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11942467Abstract: A semiconductor structure includes a first metal-dielectric-metal layer, a first dielectric layer, a first conductive layer, a second conductive layer, and a second dielectric layer. The first metal-dielectric-metal layer includes a plurality of first fingers, a plurality of second fingers, and a first dielectric material. The first fingers are electrically connected to a first voltage. The second fingers are electrically connected to a second voltage different from the first voltage, and the first fingers and the second fingers are arranged in parallel and staggeredly. The first dielectric material is between the first fingers and the second fingers. The first dielectric layer is over the first metal-dielectric-metal layer. The first conductive layer is over the first dielectric layer. The second conductive layer is over the first conductive layer. The second dielectric layer is between the first conductive layer and the second conductive layer.Type: GrantFiled: June 18, 2021Date of Patent: March 26, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: I-Sheng Chen, Yi-Jing Li, Chia-Ming Hsu, Wan-Lin Tsai, Clement Hsingjen Wann
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Patent number: 11030948Abstract: The disclosure provides a display panel including first pixel structures, second pixel structures, first signal lines, second signal lines, a first driving circuit, and a second driving circuit. The first signal lines and the first pixel structures are disposed in a first display area and electrically connected. The second signal lines and the second pixel structures are disposed in a second display area and electrically connected. The first display area and the second display area are arranged in a first direction. The first signal lines and the second signal lines are arranged in a second direction. The first direction and the second direction are perpendicular. The first signal lines and the second signal lines are structurally separated. The first drive circuit is electrically connected to the first signal lines. The second driving circuit is electrically independent from the first driving circuit and electrically connected to the second signal lines.Type: GrantFiled: May 23, 2019Date of Patent: June 8, 2021Assignee: Au Optronics CorporationInventors: Yung-Chih Chen, Wan-Lin Chen, Tsung-Ying Ke, Li-Chih Hsu, Ya-Ting Hsu, Keh-Long Hwu, Wan-Tsang Wang, Chun-Hsin Liu, Chih-Ling Hsueh
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Patent number: 10950163Abstract: A pixel circuit includes a driving circuit, a lighting element, and multiple switching circuits. The driving circuit is configured to provide a driving current to a first node. A first terminal of the lighting element is coupled with a second node. A second terminal of the lighting element is configured to receive a system low voltage. The multiple switching circuits are coupled between the first node and the second node in a parallel connection, and configured to correspondingly receive multiple emission control signals and at least one grayscale control signal. During each frame, the multiple emission control signals provide multiple pulses, and the multiple pulses do not mutually overlapping in time sequence, so that the multiple switching circuits selectively couple the first node to the second node according to the multiple pulses and the at least one grayscale control signal.Type: GrantFiled: October 21, 2019Date of Patent: March 16, 2021Assignee: AU OPTRONICS CORPORATIONInventors: Po-Chun Lai, Wei-Ting Wu, Syuan Shih, Wan-Lin Chen, Ming-Yuan Tang, Wei-Hsuan Chang, Yung-Chih Chen
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Publication number: 20200394948Abstract: A pixel circuit includes a driving circuit, a lighting element, and multiple switching circuits. The driving circuit is configured to provide a driving current to a first node. A first terminal of the lighting element is coupled with a second node. A second terminal of the lighting element is configured to receive a system low voltage. The multiple switching circuits are coupled between the first node and the second node in a parallel connection, and configured to correspondingly receive multiple emission control signals and at least one grayscale control signal. During each frame, the multiple emission control signals provide multiple pulses, and the multiple pulses do not mutually overlapping in time sequence, so that the multiple switching circuits selectively couple the first node to the second node according to the multiple pulses and the at least one grayscale control signal.Type: ApplicationFiled: October 21, 2019Publication date: December 17, 2020Inventors: Po-Chun LAI, Wei-Ting WU, Syuan SHIH, Wan-Lin CHEN, Ming-Yuan TANG, Wei-Hsuan CHANG, Yung-Chih CHEN
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Patent number: 10825383Abstract: A display device including a first substrate, pixel structures, a second substrate, first signal lines, and second signal lines is provided. The pixel structures are disposed on a first surface of the first substrate. Each of the pixel structures includes a switch element and a pixel electrode. The switch element has a first terminal, a second terminal, and a control terminal. The pixel electrode is electrically connected to the second terminal of the switch element. The second substrate is disposed under a second surface of the first substrate. The first signal lines and the second signal lines are disposed on the second substrate. The first terminals and the control terminals of the switch elements of the pixel structures are respectively electrically connected to the first signal lines and the second signal lines, wherein the first signal lines are substantially parallel to the second signal lines.Type: GrantFiled: May 14, 2019Date of Patent: November 3, 2020Assignee: Au Optronics CorporationInventors: Li-Chih Hsu, Yung-Chih Chen, Chun-Hsin Liu, Ya-Ting Hsu, Wan-Lin Chen, Wan-Tsang Wang, Tsung-Ying Ke, Keh-Long Hwu
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Publication number: 20200193900Abstract: The disclosure provides a display panel including first pixel structures, second pixel structures, first signal lines, second signal lines, a first driving circuit, and a second driving circuit. The first signal lines and the first pixel structures are disposed in a first display area and electrically connected. The second signal lines and the second pixel structures are disposed in a second display area and electrically connected. The first display area and the second display area are arranged in a first direction. The first signal lines and the second signal lines are arranged in a second direction. The first direction and the second direction are perpendicular. The first signal lines and the second signal lines are structurally separated. The first drive circuit is electrically connected to the first signal lines. The second driving circuit is electrically independent from the first driving circuit and electrically connected to the second signal lines.Type: ApplicationFiled: May 23, 2019Publication date: June 18, 2020Applicant: Au Optronics CorporationInventors: Yung-Chih Chen, Wan-Lin Chen, Tsung-Ying Ke, Li-Chih Hsu, Ya-Ting Hsu, Keh-Long Hwu, Wan-Tsang Wang, Chun-Hsin Liu, Chih-Ling Hsueh
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Publication number: 20200160783Abstract: A display device including a first substrate, pixel structures, a second substrate, first signal lines, and second signal lines is provided. The pixel structures are disposed on a first surface of the first substrate. Each of the pixel structures includes a switch element and a pixel electrode. The switch element has a first terminal, a second terminal, and a control terminal. The pixel electrode is electrically connected to the second terminal of the switch element. The second substrate is disposed under a second surface of the first substrate. The first signal lines and the second signal lines are disposed on the second substrate. The first terminals and the control terminals of the switch elements of the pixel structures are respectively electrically connected to the first signal lines and the second signal lines, wherein the first signal lines are substantially parallel to the second signal lines.Type: ApplicationFiled: May 14, 2019Publication date: May 21, 2020Applicant: Au Optronics CorporationInventors: Li-Chih Hsu, Yung-Chih Chen, Chun-Hsin Liu, Ya-Ting Hsu, Wan-Lin Chen, Wan-Tsang Wang, Tsung-Ying Ke, Keh-Long Hwu
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Patent number: 9865472Abstract: A method of etching features into a silicon layer with a steady-state gas flow is provided. An etch gas comprising an oxygen containing gas and a fluorine containing gas is provided. A plasma is provided from the etch gas. Then, the flow of the etch gas is stopped.Type: GrantFiled: April 20, 2016Date of Patent: January 9, 2018Assignee: Lam Research CorporationInventors: Robert Chebi, Frank Lin, Jaroslaw W. Winniczek, Wan-Lin Chen, Erin Moore, Lily Zheng, Stephan Lassig, Jeff Bogart, Camelia Rusu
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Publication number: 20160233102Abstract: A method of etching features into a silicon layer with a steady-state gas flow is provided. An etch gas comprising an oxygen containing gas and a fluorine containing gas is provided. A plasma is provided from the etch gas. Then, the flow of the etch gas is stopped.Type: ApplicationFiled: April 20, 2016Publication date: August 11, 2016Inventors: Robert CHEBI, Frank LIN, Jaroslaw W. WINNICZEK, Wan-Lin CHEN, Erin MOORE, Lily ZHENG, Stephan LASSIG, Jeff BOGART, Camelia RUSU
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Patent number: 9330926Abstract: A method of etching features into a silicon layer with a steady-state gas flow is provided. An etch gas comprising an oxygen containing gas and a fluorine containing gas is provided. A plasma is provided from the etch gas. Then, the flow of the etch gas is stopped.Type: GrantFiled: December 18, 2008Date of Patent: May 3, 2016Assignee: Lam Research CorporationInventors: Robert Chebi, Frank Lin, Jaroslaw W. Winniczek, Wan-Lin Chen, Erin McDonnell, Lily Zheng, Stephan Lassig, Jeff Bogart, Camelia Rusu
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Publication number: 20130280627Abstract: A hydrogen-purifying device is suitable for a fuel cell (FC). The hydrogen-purifying device includes a guiding tank, a first water-absorbing material, a porous filter material and a second water-absorbing material. The guiding tank is connected to a hydrogen-generating device and a fuel cell. The hydrogen-generating device generates hydrogen, moisture mixed with the hydrogen and impurities mixed with the hydrogen. The first water-absorbing material, the porous filter material and the second water-absorbing material are disposed in the guiding tank. The hydrogen passes through the first water-absorbing material to remove a part of the moisture. Then, the hydrogen further passes through the porous filter material to remove the impurity. After that, the hydrogen further passes through the second water-absorbing material to remove another part of the moisture and arrives at the fuel cell.Type: ApplicationFiled: April 15, 2013Publication date: October 24, 2013Applicant: YOUNG GREEN ENERGY CO.Inventors: Po-Kuei Chou, Tsai-Hsin Cheng, Din-Sun Ju, Wan-Lin Chen
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Publication number: 20090184089Abstract: A method of etching features into a silicon layer with a steady-state gas flow is provided. An etch gas comprising an oxygen containing gas and a fluorine containing gas is provided. A plasma is provided from the etch gas. Then, the flow of the etch gas is stopped.Type: ApplicationFiled: December 18, 2008Publication date: July 23, 2009Applicant: LAM RESEARCH CORPORATIONInventors: Robert CHEBI, Frank LIN, Jaroslaw W. WINNICZEK, Wan-Lin CHEN, Erin MCDONNELL, Lily ZHENG, Stephan LASSIG, Jeff BOGART, Camelia RUSU
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Patent number: 7541291Abstract: A feature in a layer is provided. A photoresist layer is formed over the layer. The photoresist layer is patterned to form photoresist features with photoresist sidewalls, where the photoresist features have a first critical dimension. A conformal layer is deposited over the sidewalls of the photoresist features to reduce the critical dimensions of the photoresist features. Features are etched into the layer, wherein the layer features have a second critical dimension, which is less than the first critical dimension.Type: GrantFiled: June 22, 2007Date of Patent: June 2, 2009Assignee: Lam Research CorporationInventors: Sean S. Kang, Sangheon Lee, Wan-Lin Chen, Eric A. Hudson, S. M. Reza Sadjadi, Gan Ming Zhao
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Patent number: 7347915Abstract: A method for creating semiconductor devices by etching a layer over a wafer is provided. A photoresist layer is provided on a wafer. The photoresist layer is patterned. The wafer is placed in a process chamber. The photoresist is hardened by providing a hardening plasma containing high energy electrons in the process chamber to harden the photoresist layer, wherein the high energy electrons have a density. The layer is etched within the process chamber with an etching plasma, where a density of high energy electrons in the etching plasma is less than the density of high energy electrons in the hardening plasma.Type: GrantFiled: January 5, 2006Date of Patent: March 25, 2008Assignee: LAM Research CorporationInventors: Douglas L. Keil, Wan-Lin Chen, Eric A. Hudson, S. M. Reza Sadjadi, Mark H. Wilcoxson, Andrew D. Bailey, III
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Publication number: 20070293050Abstract: A feature in a layer is provided. A photoresist layer is formed over the layer. The photoresist layer is patterned to form photoresist features with photoresist sidewalls, where the photoresist features have a first critical dimension. A conformal layer is deposited over the sidewalls of the photoresist features to reduce the critical dimensions of the photoresist features. Features are etched into the layer, wherein the layer features have a second critical dimension, which is less than the first critical dimension.Type: ApplicationFiled: June 22, 2007Publication date: December 20, 2007Inventors: Sean Kang, Sangheon Lee, Wan-Lin Chen, Eric Hudson, S.M. Sadjadi, Gan Zhao
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Patent number: 7250371Abstract: A feature in a layer is provided. A photoresist layer is formed over the layer. The photoresist layer is patterned to form photoresist features with photoresist sidewalls, where the photoresist features have a first critical dimension. A conformal layer is deposited over the sidewalls of the photoresist features to reduce the critical dimensions of the photoresist features. Features are etched into the layer, wherein the layer features have a second critical dimension, which is less than the first critical dimension.Type: GrantFiled: August 26, 2003Date of Patent: July 31, 2007Assignee: Lam Research CorporationInventors: Sean S. Kang, Sangheon Lee, Wan-Lin Chen, Eric A. Hudson, S. M. Reza Sadjadi, Gan Ming Zhao
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Patent number: 7226869Abstract: Methods for forming a protective polymeric coating on a silicon or silicon-carbide electrode of a plasma processing chamber are provided. The polymeric coating provides protection to the underlying surface of the electrode with respect to exposure to constituents of plasma and gaseous reactants. The methods can be performed during a process of cleaning the chamber, or during a process for etching a semiconductor substrate in the chamber.Type: GrantFiled: October 29, 2004Date of Patent: June 5, 2007Assignee: Lam Research CorporationInventors: Kenji Takeshita, Tsuyoshi Aso, Seiji Kawaguchi, Thomas McClard, Wan-Lin Chen, Enrico Magni, Michael Kelly, Michelle Lupan, Robert Hefty
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Patent number: 7192531Abstract: A method for forming damascene features in a dielectric layer over a barrier layer over a substrate is provided. A plurality of vias are etched in the dielectric layer to the barrier layer with a plasma etching process in the plasma processing chamber. A patterned photoresist layer is formed with a trench pattern. Within a single plasma process chamber a combination via plug deposition to form plugs in the vias over the barrier layer and trench etch is provided.Type: GrantFiled: June 24, 2003Date of Patent: March 20, 2007Assignee: Lam Research CorporationInventors: Sean S. Kang, Sangheon Lee, Wan-Lin Chen, Eric A. Hudson, Reza Sadjadi
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Publication number: 20060091104Abstract: Methods for forming a protective polymeric coating on a silicon or silicon-carbide electrode of a plasma processing chamber are provided. The polymeric coating provides protection to the underlying surface of the electrode with respect to exposure to constituents of plasma and gaseous reactants. The methods can be performed during a process of cleaning the chamber, or during a process for etching a semiconductor substrate in the chamber.Type: ApplicationFiled: October 29, 2004Publication date: May 4, 2006Inventors: Kenji Takeshita, Tsuyoshi Aso, Seiji Kawaguchi, Thomas McClard, Wan-Lin Chen, Enrico Magni, Michael Kelly, Michelle Lupan, Robert Hefty
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Patent number: 7022611Abstract: A method for creating semiconductor devices by etching a layer over a wafer is provided. A photoresist layer is provided on a wafer. The photoresist layer is patterned. The wafer is placed in a process chamber. The photoresist is hardened by providing a hardening plasma containing high energy electrons in the process chamber to harden the photoresist layer, wherein the high energy electrons have a density. The layer is etched within the process chamber with an etching plasma, where a density of high energy electrons in the etching plasma is less than the density of high energy electrons in the hardening plasma.Type: GrantFiled: April 28, 2003Date of Patent: April 4, 2006Assignee: Lam Research CorporationInventors: Douglas L. Keil, Wan-Lin Chen, Eric A. Hudson, S. M. Reza Sadjadi, Mark H. Wilcoxson, Andrew D. Bailey, III