Patents by Inventor Wan-Ling Yu

Wan-Ling Yu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8723313
    Abstract: A semiconductor package structure and a method for manufacturing the same are provided, in which a semiconductor die is disposed in a spacer structure for packaging, and a connection pad, a first metallic layer, an insulating layer, a wiring layer, a pin base, a conductive via and a metallic bump are formed on the semiconductor die, wherein the wiring layer can be formed as a single layer or multiple layers, and the connection pad is electrically connected with an outer pin. Moreover, the positioning structures are also formed to overcome the conventional misalignment problems caused by the thermal expansion and the cooling contraction. The alignment of the conductive via with the connection pad can be more accurately achieved, which ensures that the connection pad is reliably connected with the outer pin.
    Type: Grant
    Filed: January 14, 2012
    Date of Patent: May 13, 2014
    Inventor: Wan-Ling Yu
  • Publication number: 20130181341
    Abstract: A semiconductor package structure and a method for manufacturing the same are provided, in which a semiconductor die is disposed in a spacer structure for packaging, and a connection pad, a first metallic layer, an insulating layer, a wiring layer, a pin base, a conductive via and a metallic bump are formed on the semiconductor die, wherein the wiring layer can be formed as a single layer or multiple layers, and the connection pad is electrically connected with an outer pin. Moreover, the positioning structures are also formed to overcome the conventional misalignment problems caused by the thermal expansion and the cooling contraction. The alignment of the conductive via with the connection pad can be more accurately achieved, which ensures that the connection pad is reliably connected with the outer pin.
    Type: Application
    Filed: January 14, 2012
    Publication date: July 18, 2013
    Inventor: Wan-Ling Yu
  • Patent number: 7968446
    Abstract: The metallic bump is directly formed on a semiconductor wafer's I/O pad without UBM. First, a zinc layer is formed on the I/O pad or an anti-oxidation layer of the I/O pad is selectively etched off. Then, an isolative layer and a copper foil are arranged sequentially in this order above the I/O pad. The isolative layer is originally in a liquid state or in a temporarily solid state and later permanently solidified. Then, a via above the I/O pad is formed by removing part of the isolative layer and the cooper foil. Subsequently, A thin metallic layer connecting the copper foil and the I/O pad is formed in the via and a plating resist on the copper foil is formed. Then, a metallic bump is formed from the via whose height is controlled by the plating resist. Finally, the plating resist and the copper foil are removed.
    Type: Grant
    Filed: October 6, 2008
    Date of Patent: June 28, 2011
    Inventor: Wan-Ling Yu
  • Publication number: 20110086505
    Abstract: The metallic bump is directly formed on a semiconductor wafer's I/O pad without UBM. First, a zinc layer is formed on the I/O pad or an anti-oxidation layer of the I/O pad is selectively etched off. Then, an isolative layer and a copper foil are arranged sequentially in this order above the I/O pad. The isolative layer is originally in a liquid state or in a temporarily solid state and later permanently solidified. Then, a via above the I/O pad is formed by removing part of the isolative layer and the cooper foil. Subsequently, a thin metallic layer connecting the copper foil and the I/O pad is formed in the via and a plating resist on the copper foil is formed. Then, a metallic bump is formed from the via whose height is controlled by the plating resist. Finally, the plating resist and the copper foil are removed.
    Type: Application
    Filed: December 17, 2010
    Publication date: April 14, 2011
    Inventor: Wan-Ling Yu
  • Publication number: 20100320560
    Abstract: The metallic bump is directly formed on a semiconductor wafer's I/O pad without UBM. First, a zinc layer is formed on the I/O pad or an anti-oxidation layer of the I/O pad is selectively etched off. Then, an isolative layer and a copper foil are arranged sequentially in this order above the I/O pad. The isolative layer is originally in a liquid state or in a temporarily solid state and later permanently solidified. Then, a via above the I/O pad is formed by removing part of the isolative layer and the cooper foil. Subsequently, A thin metallic layer connecting the copper foil and the I/O pad is formed in the via and a plating resist on the copper foil is formed. Then, a metallic bump is formed from the via whose height is controlled by the plating resist. Finally, the plating resist and the copper foil are removed.
    Type: Application
    Filed: August 28, 2010
    Publication date: December 23, 2010
    Inventor: Wan-Ling Yu
  • Patent number: 7733627
    Abstract: The embedded capacitor of the present invention contains a power plate, a ground plate, and a dielectric layer vertically sandwiched between the power and ground plates. Both the power and ground plates are divided laterally into a number of smaller plates with appropriate gaps therebetween; and, as such, cracks in the dielectric layers are limited to happen between gaps only. The smaller plates are then electrically connected by connectors in the gaps. The connectors for the power plate and the connectors for the ground plate are not vertically overlapped so that they do not appear simultaneously at the two ends of the cracks simultaneously.
    Type: Grant
    Filed: September 24, 2007
    Date of Patent: June 8, 2010
    Inventor: Wan-Ling Yu
  • Patent number: 7713860
    Abstract: The method mainly contains the following steps. First, an UBM is formed on a top side of a semiconductor's I/O pad. An isolative layer and a metallic foil are sequentially arranged in this order on the UBM. Then, a via is formed to expose the top surface of the UBM. Subsequently, a thin metallic layer is formed in the via and a resist is formed on the metallic foil. Then, by using the metallic foil and the thin metallic layer as an electrode to conduct electrical current, a metallic bump is formed using electroplating in the via on the top side of the UBM. Finally, the resist and the metallic foil are removed and the formation of the metallic bump is completed.
    Type: Grant
    Filed: October 13, 2007
    Date of Patent: May 11, 2010
    Inventor: Wan-Ling Yu
  • Patent number: 7713861
    Abstract: The method mainly contains the following steps. First, an UBM is formed on a top side of a semiconductor's I/O pad. An isolative layer and a metallic foil are sequentially arranged in this order on the UBM. Then, a via is formed to expose the top surface of the UBM. Subsequently, a thin metallic layer is formed in the via and a resist is formed on the metallic foil. Then, by using the metallic foil and the thin metallic layer as an electrode to conduct electrical current, a metallic bump is formed using electroplating in the via on the top side of the UBM. Finally, the resist and the metallic foil are removed and the formation of the metallic bump is completed. Optionally coating on bump may be needed for certain chosen bump materials.
    Type: Grant
    Filed: January 18, 2008
    Date of Patent: May 11, 2010
    Inventor: Wan-Ling Yu
  • Publication number: 20100084763
    Abstract: The metallic bump is directly formed on a semiconductor wafer's I/O pad without UBM. First, a zinc layer is formed on the I/O pad or an anti-oxidation layer of the I/O pad is selectively etched off. Then, an isolative layer and a copper foil are arranged sequentially in this order above the I/O pad. The isolative layer is originally in a liquid state or in a temporarily solid state and later permanently solidified. Then, a via above the I/O pad is formed by removing part of the isolative layer and the cooper foil. Subsequently, A thin metallic layer connecting the copper foil and the I/O pad is formed in the via and a plating resist on the copper foil is formed. Then, a metallic bump is formed from the via whose height is controlled by the plating resist. Finally, the plating resist and the copper foil are removed.
    Type: Application
    Filed: October 6, 2008
    Publication date: April 8, 2010
    Inventor: Wan-Ling Yu
  • Publication number: 20090098724
    Abstract: The method mainly contains the following steps. First, an UBM is formed on a top side of a semiconductor's I/O pad. An isolative layer and a metallic foil are sequentially arranged in this order on the UBM. Then, a via is formed to expose the top surface of the UBM. Subsequently, a thin metallic layer is formed in the via and a resist is formed on the metallic foil. Then, by using the metallic foil and the thin metallic layer as an electrode to conduct electrical current, a metallic bump is formed using electroplating in the via on the top side of the UBM. Finally, the resist and the metallic foil are removed and the formation of the metallic bump is completed. Optionally coating on bump may be needed for certain chosen bump materials.
    Type: Application
    Filed: January 18, 2008
    Publication date: April 16, 2009
    Inventor: Wan-Ling Yu
  • Publication number: 20090098723
    Abstract: The method mainly contains the following steps. First, an UBM is formed on a top side of a semiconductor's I/O pad. An isolative layer and a metallic foil are sequentially arranged in this order on the UBM. Then, a via is formed to expose the top surface of the UBM. Subsequently, a thin metallic layer is formed in the via and a resist is formed on the metallic foil. Then, by using the metallic foil and the thin metallic layer as an electrode to conduct electrical current, a metallic bump is formed using electroplating in the via on the top side of the UBM. Finally, the resist and the metallic foil are removed and the formation of the metallic bump is completed.
    Type: Application
    Filed: October 13, 2007
    Publication date: April 16, 2009
    Inventor: Wan-Ling Yu
  • Publication number: 20090080139
    Abstract: The embedded capacitor of the present invention contains a power plate, a ground plate, and a dielectric layer vertically sandwiched between the power and ground plates. Both the power and ground plates are divided laterally into a number of smaller plates with appropriate gaps therebetween; and, as such, cracks in the dielectric layers are limited to happen between gaps only. The smaller plates are then electrically connected by connectors in the gaps. The connectors for the power plate and the connectors for the ground plate are not vertically overlapped so that they do not appear simultaneously at the two ends of the cracks simultaneously.
    Type: Application
    Filed: September 24, 2007
    Publication date: March 26, 2009
    Inventor: Wan-Ling Yu