Abstract: Systems, apparatus and methods are provided for determining whether data accessed by the command in a storage system is hot or cold. An apparatus may include a first interface to be coupled to a host and a storage controller configured to: receive a command that contains an address in a data storage system; generate a set of hash addresses for the address; for each hash address of the set of hash addresses: obtain a stored hotness score associated with the hash address, update the stored hotness score to generate an updated hotness score associated with the hash address, and determine that the updated hotness score is above a hotness threshold; and determine that the address is hot.

Abstract: A cargo bicycle having at least a frame, rear wheel, and rear carrier rack, comprising a rear safety cage, pair of footboards and passenger cabin having a canopy and box is provided. The rear safety cage is mounted to the frame. The passenger cabin is mounted to the rear safety cage, rear carrier rack and pair of footboards and forms an interior passenger space for accommodating passengers and protecting passengers from natural or human-made environmental elements. The canopy forms an upper interior space. The box forms a lower interior space and a pair of lower interior side spaces extending outwardly from the lower interior space, straddling the rear wheel. Each of the pair of lower interior side spaces is a self-contained vessel, further protecting lower extremities of passengers from components of the cargo bicycle and debris during operation of the cargo bicycle.

Abstract: Systems, apparatus and methods are provided for determining whether data accessed by the command in a storage system is hot or cold. An apparatus may include a first interface to be coupled to a host and a storage controller configured to: receive a command that contains an address in a data storage system; generate a set of hash addresses for the address; for each hash address of the set of hash addresses: obtain a stored hotness score associated with the hash address, update the stored hotness score to generate an updated hotness score associated with the hash address, and determine that the updated hotness score is above a hotness threshold; and determine that the address is hot.

Abstract: Systems, apparatus and methods are provided for performing computations of a neural network using hardware computational circuitry. An apparatus may include a controller, a configuration buffer and a data buffer. The controller may be configured to dispatch computing tasks of a neural network, load configurations into the configuration buffer and load input data and parameters including weights and biases into the data buffer. The apparatus may also include a multiply-accumulate (MAC) layer. The configurations may include at least one FNN configuration. The MAC layer may apply the at least one FNN configuration, which includes settings for a FNN operation topology for the MAC layer to perform computations for at least one FNN layer. Optionally, the neural network may be a CNN and the configurations may further include at least one CNN configuration for the MAC layer to perform computations for at least one CNN layer.

Abstract: A cargo bicycle having at least a frame, rear wheel, and rear carrier rack, comprising a rear safety cage, pair of footboards and passenger cabin having a canopy and box is provided. The rear safety cage is mounted to the frame. The passenger cabin is mounted to the rear safety cage, rear carrier rack and pair of footboards and forms an interior passenger space for accommodating passengers and protecting passengers from natural or human-made environmental elements. The canopy forms an upper interior space. The box forms a lower interior space and a pair of lower interior side spaces extending outwardly from the lower interior space, straddling the rear wheel. Each of the pair of lower interior side spaces is a self-contained vessel, further protecting lower extremities of passengers from components of the cargo bicycle and debris during operation of the cargo bicycle.

Abstract: The present disclosure is directed to systems and methods for cell placement. In embodiments, the methods include placing a plurality of cells selected from a cell library in a chip design to produce a first cell placement and determining whether the first cell placement satisfies design demands. In further embodiments, the method also includes rearranging a first cell to abut the first cell with a second cell when the first cell placement fails to satisfy design demands. In still further embodiments, the first cell is rearranged until a second cell placement providing a minimum metal route between the first and second cells is determined. In various embodiments, the method further includes generating a design layout based on the second cell placement and outputting the design layout to a machine readable storage medium. The outputted layout is used to manufacture a set of masks used in chip fabrication processes.

Abstract: The present disclosure is directed to systems and methods for cell placement. In embodiments, the methods include placing a plurality of cells selected from a cell library in a chip design to produce a first cell placement and determining whether the first cell placement satisfies design demands. In further embodiments, the method also includes rearranging a first cell to abut the first cell with a second cell when the first cell placement fails to satisfy design demands. In still further embodiments, the first cell is rearranged until a second cell placement providing a minimum metal route between the first and second cells is determined. In various embodiments, the method further includes generating a design layout based on the second cell placement and outputting the design layout to a machine readable storage medium. The outputted layout is used to manufacture a set of masks used in chip fabrication processes.

Abstract: An integrated circuit (IC) design system includes a processor; and a non-transitory computer readable medium connected to the processor. The non-transitory computer readable medium is configured to store a configuration file containing a custom IC design parameter, to store a process design kit (PDK) containing a default IC design parameter, and to store instructions for execution by the processor. The instructions for execution by the process include instructions for extracting the custom IC design parameter from the configuration file. The instructions for execution by the process further include instructions for overwriting the default IC design parameter in the PDK with the custom IC design parameter. The instructions for execution by the process further include instructions for creating an IC design file using a module in the PDK using the custom IC design parameter in place of the default IC design parameter.

Abstract: An integrated circuit (IC) design system includes a processor; and a non-transitory computer readable medium connected to the processor. The non-transitory computer readable medium is configured to store a configuration file containing a custom IC design parameter, to store a process design kit (PDK) containing a default IC design parameter, and to store instructions for execution by the processor. The instructions for execution by the process include instructions for extracting the custom IC design parameter from the configuration file. The instructions for execution by the process further include instructions for overwriting the default IC design parameter in the PDK with the custom IC design parameter. The instructions for execution by the process further include instructions for creating an IC design file using a module in the PDK using the custom IC design parameter in place of the default IC design parameter.

Abstract: An integrated circuit design method includes extracting a custom IC design parameter from a configuration file using a design customization module (DCM) and creating an IC design file with a module in a processor design kit (PDK) using the custom IC design parameter.

Abstract: An integrated circuit design method includes extracting a custom IC design parameter from a configuration file using a design customization module (DCM) and creating an IC design file with a module in a processor design kit (PDK) using the custom IC design parameter.

Abstract: A digital-to-analog converter includes: a resistor string; a plurality of first switches each connected between an output node and a corresponding one of first endmost, second endmost and intermediate nodes of the resistor string; a decoding unit adapted for converting a higher-order portion of a digital signal into a decoder signal used to control the first switches such that one of which is selected according to the higher-order portion to connect the corresponding one of the nodes to the output node; and first and second voltage-setting units adapted to be connected between one of first and second reference voltage sources and one of the first and second endmost nodes of the resistor string, and operable in response to a lower-order portion of the digital signal to adjust voltages at the first endmost, second endmost and intermediate nodes of the resistor string according to the lower-order portion of the digital signal.

Abstract: A digital-to-analog converter includes: a resistor string; a plurality of first switches each connected between an output node and a corresponding one of first endmost, second endmost and intermediate nodes of the resistor string; a decoding unit adapted for converting a higher-order portion of a digital signal into a decoder signal used to control the first switches such that one of which is selected according to the higher-order portion to connect the corresponding one of the nodes to the output node; and first and second voltage-setting units adapted to be connected between one of first and second reference voltage sources and one of the first and second endmost nodes of the resistor string, and operable in response to a lower-order portion of the digital signal to adjust voltages at the first endmost, second endmost and intermediate nodes of the resistor string according to the lower-order portion of the digital signal.