Abstract: The storage device includes a memory controller and a plurality of banks, each of the plurality of banks including a plurality of memory devices. Each of the plurality of memory devices includes: a data selector for selecting and outputting data of a memory device that is included in any one of the plurality of banks based on a bank select signal; a latch unit for storing the data that is output from the data selector; and a transmission control signal generator for generating the bank select signal such that the data that is stored in the latch unit is sequentially output.

Abstract: An address counting circuit includes a shared address counting circuit configured to generate a first shared address and a second shared address by counting an external start address at a first edge and a second edge of a counting clock signal and a latch circuit including a plurality of latches configured to share the first shared address and the second shared address, respectively and generate a plurality of column addresses by latching the first shared address and second shared address according to a plurality of latch clock signals.

Abstract: The storage device includes a memory controller and a plurality of banks, each of the plurality of banks including a plurality of memory devices. Each of the plurality of memory devices includes: a data selector for selecting and outputting data of a memory device that is included in any one of the plurality of banks based on a bank select signal; a latch unit for storing the data that is output from the data selector; and a transmission control signal generator for generating the bank select signal such that the data that is stored in the latch unit is sequentially output.

Abstract: An address counting circuit includes a shared address counting circuit configured to generate a first shared address and a second shared address by counting an external start address at a first edge and a second edge of a counting clock signal and a latch circuit including a plurality of latches configured to share the first shared address and the second shared address, respectively and generate a plurality of column addresses by latching the first shared address and second shared address according to a plurality of latch clock signals.

Abstract: A semiconductor memory device includes a cache latch group including a plurality of even latch stages and a plurality of odd latch stages arranged alternately with each other; and a sense amplifier group coupled to the cache latch group through a plurality of first bit out lines respectively corresponding to the plurality of even latch stages and through a plurality of second bit out lines respectively corresponding to the plurality of odd latch stages.

Abstract: A semiconductor memory device includes a cache latch group including a plurality of even latch stages and a plurality of odd latch stages arranged alternately with each other; and a sense amplifier group coupled to the cache latch group through a plurality of first bit out lines respectively corresponding to the plurality of even latch stages and through a plurality of second bit out lines respectively corresponding to the plurality of odd latch stages.

Abstract: The present disclosure relates to a memory device including a BIST circuit and an operating method thereof. The memory device includes a comparison circuit comparing test pattern data with sensing data to generate a comparison signal, a status information generating circuit generating a fail mask signal by marking data in which a failure occurs in the sensing data in response to the comparison signal, a column address generating circuit generating column addresses sequentially increasing in response to an input/output strobe signal, a latch enable signal generating circuit generating a latch enable signal in response to the fail mask signal, and an input/output circuit receiving the column addresses and selectively latching a column address in which a failure occurs among the column addresses in response to the latch enable signal.

Abstract: The present disclosure relates to a memory device including a BIST circuit and an operating method thereof. The memory device includes a comparison circuit comparing test pattern data with sensing data to generate a comparison signal, a status information generating circuit generating a fail mask signal by marking data in which a failure occurs in the sensing data in response to the comparison signal, a column address generating circuit generating column addresses sequentially increasing in response to an input/output strobe signal, a latch enable signal generating circuit generating a latch enable signal in response to the fail mask signal, and an input/output circuit receiving the column addresses and selectively latching a column address in which a failure occurs among the column addresses in response to the latch enable signal.

Abstract: Provided herein is a semiconductor memory device. The semiconductor memory device may include a plurality of planes including a plurality of memory cells, read/write circuits coupled to the plurality of planes, respectively, and temporarily storing normal data inputted from an external device, random data, and parity data, and an error correction circuit generating the random data by randomizing the normal data, generating parity data for the random data during a program operation, correcting an error of the random data by using the parity data and de-randomizing the random data during a read operation.

Abstract: Provided herein is a semiconductor memory device. The semiconductor memory device may include a plurality of planes including a plurality of memory cells, read/write circuits coupled to the plurality of planes, respectively, and temporarily storing normal data inputted from an external device, random data, and parity data, and an error correction circuit generating the random data by randomizing the normal data, generating parity data for the random data during a program operation, correcting an error of the random data by using the parity data and de-randomizing the random data during a read operation.

Abstract: A latch circuit, a receiver circuit, a semiconductor apparatus, or a system may be provided. The latch circuit may include a delay configured to delay an input signal and generate a delay signal. The latch circuit may include a control signal generator configured to enable a control signal based on the input signal and the delay signal, and disable the control signal based on a reset signal. The latch circuit may include a gating circuit configured to output, based on the control signal, the input signal and the delay signal to an output node. The latch circuit may include a latch configured to latch, based on a strobe pulse, an output of the gating circuit and generate an output signal.

Abstract: A semiconductor test device performs a test using a high-speed internal clock. The semiconductor test device includes a clock generator suitable for generating an internal clock in response to a test mode signal during a test mode, a data generator suitable for generating internal data in response to the internal clock, and a data latch circuit suitable for latching the internal data in response to the internal clock, and outputting the latched data to an internal logic circuit.

Abstract: A method of operating a memory system according to an aspect of the present disclosure includes storing first data in a memory controller; storing second data in the memory controller, wherein the second data is read from a selected page of a first memory block of a memory device; and performing a program operation for storing third data, that include the first data and the second data, in a selected page of a second memory block of the memory device.

Abstract: A semiconductor test device performs a test using a high-speed internal clock. The semiconductor test device includes a clock generator suitable for generating an internal clock in response to a test mode signal during a test mode, a data generator suitable for generating internal data in response to the internal clock, and a data latch circuit suitable for latching the internal data in response to the internal clock, and outputting the latched data to an internal logic circuit.

Abstract: A semiconductor test device performs a test using a high-speed internal clock. The semiconductor test device includes a clock generator suitable for generating an internal clock in response to a test mode signal during a test mode, a data generator suitable for generating internal data in response to the internal clock, and a data latch circuit suitable for latching the internal data in response to the internal clock, and outputting the latched data to an internal logic circuit.

Abstract: A semiconductor memory device includes a memory cell array configured to include sub memory blocks and a redundancy memory block, data line groups configured to deliver data to be programmed into the sub memory blocks and data read from the sub memory blocks, a redundancy data line group configured to deliver data to be programmed into the redundancy memory block and data read from the redundancy memory block, and switching circuits configured to couple selectively the data line groups to the redundancy data line group.

Abstract: A semiconductor test device performs a test using a high-speed internal clock. The semiconductor test device includes a clock generator suitable for generating an internal clock in response to a test mode signal during a test mode, a data generator suitable for generating internal data in response to the internal clock, and a data latch circuit suitable for latching the internal data in response to the internal clock, and outputting the latched data to an internal logic circuit.

Abstract: A reading method of a semiconductor memory device having a multi-level memory cell includes the steps of: reading flag data indicating whether the most significant bit (MSB) of data programmed in the multi-level memory cell is programmed or not; storing the read flag data; reading the least significant bit (LSB) of the data programmed in the multi-level memory cell, based on the read flag data; and reading the MSB of the data programmed in the multi-level memory cell based on the stored flag data.

Abstract: A semiconductor memory device includes a memory cell array configured to include sub memory blocks and a redundancy memory block, data line groups configured to deliver data to be programmed into the sub memory blocks and data read from the sub memory blocks, a redundancy data line group configured to deliver data to be programmed into the redundancy memory block and data read from the redundancy memory block, and switching circuits configured to couple selectively the data line groups to the redundancy data line group.

Abstract: A semiconductor memory device includes a first plane and a second plane each configured to include a plurality of memory cells, and a data transfer circuit configured to transfer first data, stored in the memory cells of the first plane, to the second plane and transfer second data, stored in the memory cells of the second plane, to the first plane when a copyback operation is performed and to transfer the first data or the second data to an I/O circuit when a read operation is performed.