Abstract: A processing element architecture adapted to a convolution comprises a plurality of processing elements and a delayed queue circuit. The plurality of processing elements includes a first processing element and a second processing element, wherein the first processing element and the second processing element perform the convolution according to a shared datum at least. The delayed queue circuit connects to the first processing element and connects to the second processing element. The delayed queue circuit receives the shared datum sent by the first processing element, and sends the shared datum to the second processing element after receiving the shared datum and waiting for a time interval.

Abstract: A deep neural network (DNN) hardware accelerator including a processing element array is disclosed. The processing element array includes a processing element array, the processing element array including a plurality of processing element groups and each of the processing element groups including a plurality of processing elements. A first network connection implementation between a first processing element group of the processing element groups and a second processing element group of the processing element groups is different from a second network connection implementation between the processing elements in the first processing element group.