Abstract: The present disclosure according to at least one embodiment provides a semiconductor test apparatus comprising: a failure memory (FM) block storing failure data, which is generated from a result of testing a semiconductor device, a buffer memory (BM) block to/in which the failure data stored in the FM block is copied/stored, and a field programmable gate array (FPGA) performing a first control operation for controlling the FM block and a second control operation for controlling the BM block.

Abstract: A semiconductor test apparatus is provided. The semiconductor test apparatus includes: a test management unit determining a test mode, generating a test signal in accordance with the determined test mode, and transmitting the test signal to fail memories; and one or more fail memory boards including the fail memory, which store fail signals generated as a result of a test conducted in accordance with the test signal and address information of the fail signals, wherein if the determined test mode is a first test mode, at least some of the failure memory boards are powered off.