Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate and a resistive element over the substrate. The semiconductor device structure also includes a thermal conductive element over the substrate. A direct projection of the thermal conductive element on a main surface of the resistive element extends across a portion of a first imaginary line and a portion of a second imaginary line of the main surface. The first imaginary line is perpendicular to the second imaginary line, and the first imaginary line and the second imaginary line intersect at a center of the main surface.

Abstract: An integrated circuit (IC) structure includes a semiconductor substrate, a bottom electrode routing, a capacitor structure, a top electrode routing. The bottom electrode routing is over the semiconductor substrate. The capacitor structure is over the bottom electrode routing. The capacitor structure includes a bottom metal layer, a middle metal layer above the bottom metal layer, and a top metal layer above the middle metal layer. When viewed in a plan view, the top metal layer has opposite straight edges extending along a first direction and opposite square wave-shaped edges connecting the opposite straight edges, the square wave-shaped edges each comprise alternating first and second segments extending along a second direction perpendicular to the first direction, and third segments each connecting adjacent two of the first and second segments, wherein the third segments extend along the first direction.

Abstract: An integrated circuit (IC) structure includes a semiconductor substrate, a bottom electrode routing, a capacitor structure, a top electrode routing. The bottom electrode routing is over the semiconductor substrate. The capacitor structure is over the bottom electrode routing. The capacitor structure includes a bottom metal layer, a middle metal layer above the bottom metal layer, and a top metal layer above the middle metal layer. When viewed in a plan view, the top metal layer has opposite straight edges extending along a first direction and opposite square wave-shaped edges connecting the opposite straight edges, the square wave-shaped edges each comprise alternating first and second segments extending along a second direction perpendicular to the first direction, and third segments each connecting adjacent two of the first and second segments, wherein the third segments extend along the first direction.

Abstract: A semiconductor device structure and method for manufacturing the same are provided. The method includes forming a first resistive element over a substrate, and the first resistive element has a first sidewall extending in a first direction and a second sidewall opposite to the first sidewall and extending in the first direction. The method further includes forming a first conductive feature and a second conductive feature over and electrically connected to the first resistive element and forming a second resistive element over the first resistive element and spaced apart from the first resistive element in a second direction. In addition, the second resistive element is located between the first sidewall and the second sidewall of the first resistive element in a top view, and the first resistive element and the second resistive element are made of different nitrogen-containing materials.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a semiconductor substrate, a first resistive element and a second resistive element over the semiconductor substrate. A topmost surface of the second resistive element is higher than a topmost surface of the first resistive element. The semiconductor device structure also includes a first conductive feature and a second conductive feature electrically connected to the first resistive element. The second resistive element is between and electrically isolated from the first conductive feature and the second conductive feature. The semiconductor device structure further includes a first dielectric layer surrounding the first conductive feature and the second conductive feature.

Abstract: Methods and semiconductor devices are described herein which eliminate the use of additional masks. A first interconnect layer is formed. A first resistive layer is formed on top of the first interconnect layer. A dielectric layer is formed on top of the first resistive layer. A second resistive layer is formed on top of the dielectric layer.

Abstract: A method (of forming a semiconductor device) includes: forming an active area structure extending in a first direction; forming gate structures over the active area structure and extending in a second direction substantially perpendicular to the first direction; forming contact-source/drain (CSD) conductors over the active area structure, interleaved with corresponding ones of the gate structures, and extending in the second direction; and forming first conductive segments in a first layer of metallization (M_lst layer) over the active area structure and extending in the first direction, the first conductive segments including a first gate-signal-carrying (GSC) conductor which overlaps the active area structure.

Abstract: Methods and semiconductor devices are described herein which eliminate the use of additional masks. A first interconnect layer is formed. A first resistive layer is formed on top of the first interconnect layer. A dielectric layer is formed on top of the first resistive layer. A second resistive layer is formed on top of the dielectric layer.

Abstract: A semiconductor device includes: an active area in a transistor layer; contact-source/drain (CSD) conductors in the transistor layer; gate conductors in the transistor layer, and interleaved with the CSD conductors; VG structures in the transistor layer, and over the active area; and a first gate-signal-carrying (GSC) conductor in an M_1st layer that is over the transistor layer, and that is over the active area; and wherein long axes correspondingly of the active area and the first GSC conductor extend substantially in a first direction; and long axes correspondingly of the CSD conductors and the gate conductors extend substantially in a second direction, the second direction being substantially perpendicular to the first direction.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate and a resistive element over the substrate. The semiconductor device structure also includes a thermal conductive element over the substrate. A direct projection of the thermal conductive element on a main surface of the resistive element extends across a portion of a first imaginary line and a portion of a second imaginary line of the main surface. The first imaginary line is perpendicular to the second imaginary line, and the first imaginary line and the second imaginary line intersect at a center of the main surface.

Abstract: An integrated circuit (IC) structure includes a semiconductor substrate, a bottom electrode routing, a capacitor structure, a top electrode routing. The bottom electrode routing is over the semiconductor substrate. The capacitor structure is over the bottom electrode routing. The capacitor structure includes a bottom metal layer, a middle metal layer above the bottom metal layer, and a top metal layer above the middle metal layer. When viewed in a plan view, the top metal layer has opposite straight edges extending along a first direction and opposite square wave-shaped edges connecting the opposite straight edges, the square wave-shaped edges each comprise alternating first and second segments extending along a second direction perpendicular to the first direction, and third segments each connecting adjacent two of the first and second segments, wherein the third segments extend along the first direction.

Abstract: A semiconductor device and method of manufacturing the same are provided. The semiconductor device includes a first active region extending along a first direction. The semiconductor device also includes a second active region extending along the first direction. The semiconductor device further includes a first gate extending along a second direction perpendicular to the first direction. The first gate has a first segment disposed between the first active region and the second active region. In addition, the semiconductor device includes a first electrical conductor extending along the second direction and across the first active region and the second active region, wherein the first segment of the first gate and the first electrical conductor are partially overlapped to form a first capacitor.

Abstract: A semiconductor device includes a substrate. A first nanosheet structure and a second nanosheet structure are disposed on the substrate. Each of the first and second nanosheet structures have at least one nanosheet forming source/drain regions and a gate structure including a conductive gate contact. A first oxide structure is disposed on the substrate between the first and second nanosheet structures. A conductive terminal is disposed in or on the first oxide structure. The conductive terminal, the first oxide structure and the gate structure of the first nanosheet structure define a capacitor.

Abstract: An integrated circuit (IC) including a plurality of finfet cells designed with digital circuit design rules to provide smaller finfet cells with decreased cell heights, and analog circuit cell structures including first finfet cells of the plurality of finfet cells and including at least one cut metal layer. The smaller finfet cells with decreased cell heights provide a first shorter metal track in one direction and the at least one cut metal layer provides a second shorter metal track in another direction to increase maximum electromigration currents in the integrated circuit.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a semiconductor substrate, a gate stack, and an interconnect structure over the gate stack and the semiconductor substrate. The semiconductor device structure also includes a resistive element over the interconnect structure, and the resistive element is directly above the gate stack. The semiconductor device structure further includes a thermal conductive element over the interconnect structure. The thermal conductive element at least partially overlaps the resistive element. In addition, the semiconductor device structure includes a dielectric layer separating the thermal conductive element from the resistive element.

Abstract: A method of manufacturing a semiconductor device based on a dual-architecture-compatible design includes: forming transistor components of in a transistor (TR) layer; and performing one of fabricating additional components according to (A) a buried power rail (BPR) type of architecture or (B) a non-buried power rail (non-BPR) type of architecture. The step (A) includes, in corresponding sub-TR layers, forming various non-dummy sub-TR structures, and, in corresponding supra-TR layers, forming various dummy supra-TR structures which are corresponding first artifacts. The step (B) includes, in corresponding supra-TR layers, forming various non-dummy supra-TR structures and forming various dummy supra-TR structures which are corresponding second artifacts, the first and second artifacts resulting from the dual-architecture-compatible design being suitable to adaptation into the BPR type of architecture.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a semiconductor substrate, a first resistive element and a second resistive element over the semiconductor substrate. A topmost surface of the second resistive element is higher than a topmost surface of the first resistive element. The semiconductor device structure also includes a first conductive feature and a second conductive feature electrically connected to the first resistive element. The second resistive element is between and electrically isolated from the first conductive feature and the second conductive feature. The semiconductor device structure further includes a first dielectric layer surrounding the first conductive feature and the second conductive feature.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a semiconductor substrate and a first resistive element and a second resistive element over the semiconductor substrate. The semiconductor device structure also includes a first conductive feature electrically connected to the first resistive element and a second conductive feature electrically connected to the second resistive element. The semiconductor device structure further includes a dielectric layer surrounding the first conductive feature and the second conductive feature.

Abstract: Methods and semiconductor devices are described herein which eliminate the use of additional masks. A first interconnect layer is formed. A first resistive layer is formed on top of the first interconnect layer. A dielectric layer is formed on top of the first resistive layer. A second resistive layer is formed on top of the dielectric layer.

Abstract: A semiconductor device includes: an active area in a transistor layer; contact-source/drain (CSD) conductors in the transistor layer; gate conductors in the transistor layer, and interleaved with the CSD conductors; VG structures in the transistor layer, and over the active area; and a first gate-signal-carrying (GSC) conductor in an M_1st layer that is over the transistor layer, and that is over the active area; and wherein long axes correspondingly of the active area and the first GSC conductor extend substantially in a first direction; and long axes correspondingly of the CSD conductors and the gate conductors extend substantially in a second direction, the second direction being substantially perpendicular to the first direction.