Patents by Inventor Wan-Ting SHIH
Wan-Ting SHIH has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11532577Abstract: An embodiment is a method including depositing a first dielectric layer over a molding compound and a chip and patterning a first opening in the first dielectric layer to expose a contact of the chip. A first metallization layer is deposited over the first dielectric layer and in the first opening, where a portion of the first metallization layer in the first opening has a flat top. A second dielectric layer is deposited over the first metallization layer and the first dielectric layer. A second metallization layer is deposited in a second opening in the second dielectric layer, where the second metallization layer does not have a flat top within the second opening.Type: GrantFiled: August 10, 2020Date of Patent: December 20, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Wan-Ting Shih, Nai-Wei Liu, Jing-Cheng Lin, Cheng-Lin Huang
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Patent number: 10911113Abstract: A communication system and a codec method based on deep learning and known channel state information (CSI) are provided. The communication system includes: a first electronic apparatus including a known first link CSI and a CSI encoder having a deep learning function; and a second electronic apparatus including a known second link CSI and a CSI decoder having a deep learning function. The first and second link CSIs have a correlation or a similarity. The CSI encoder of the first electronic apparatus encodes or compresses the first link CSI into the first codeword, and feeds the first codeword back to the second electronic apparatus via a feedback link. The CSI decoder of the second electronic apparatus encodes or compresses the second link CSI into a second codeword, and decodes or restores the first link CSI of the first electronic apparatus based on the first codeword and the second codeword.Type: GrantFiled: March 15, 2019Date of Patent: February 2, 2021Assignee: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTEInventors: Chao-Kai Wen, Wan-Ting Shih, Ren-Jr Chen
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Patent number: 10867897Abstract: A method of forming a PoP device comprises placing an adhesive layer on a carrier substrate, coupling a plurality of chip packages to the adhesive layer on the carrier substrate, placing a bonding layer on the chip packages, and coupling a plurality of chips to the bonding layer on the chip packages. The method further comprises injecting a molding compound to encapsulate the chip packages and the chips on the carrier substrate, grinding the molding compound to expose a plurality of connecting elements of the chips and a plurality of second connecting elements of the chip packages, forming a redistribution layer (RDL) on the molding compound and the exposed connecting elements and second connecting elements, forming a ball grid array (BGA) on the RDL, and de-bonding the carrier substrate.Type: GrantFiled: April 13, 2018Date of Patent: December 15, 2020Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chin-Chuan Chang, Jing-Cheng Lin, Nai-Wei Liu, Wan-Ting Shih
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Publication number: 20200373264Abstract: An embodiment is a method including depositing a first dielectric layer over a molding compound and a chip and patterning a first opening in the first dielectric layer to expose a contact of the chip. A first metallization layer is deposited over the first dielectric layer and in the first opening, where a portion of the first metallization layer in the first opening has a flat top. A second dielectric layer is deposited over the first metallization layer and the first dielectric layer. A second metallization layer is deposited in a second opening in the second dielectric layer, where the second metallization layer does not have a flat top within the second opening.Type: ApplicationFiled: August 10, 2020Publication date: November 26, 2020Inventors: Wan-Ting Shih, Nai-Wei Liu, Jing-Cheng Lin, Cheng-Lin Huang
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Patent number: 10771143Abstract: A switching method for multiple antenna arrays is disclosed which including: turning on a number of antenna arrays of an electronic device, and obtaining multiple received powers of a beam signal; turning off the antenna array(s) other than the antenna array having the largest received power, and calculating multiple first power ratio parameters according to the received powers; calculating a first channel information of the antenna array which is turned on; calculating a first virtual channel information of each of the antenna arrays which are turned off according to the first channel information, the first power ratio parameter corresponding to each of the antenna arrays which are turned off and an angle mapping table; and selecting one of the antenna arrays to turn on according to the first channel information and all the first virtual channel information, and turning off the rest antenna array(s).Type: GrantFiled: December 27, 2019Date of Patent: September 8, 2020Assignee: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTEInventors: Chao-Kai Wen, Zi-Hui Shen, Wan-Ting Shih
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Patent number: 10741511Abstract: An embodiment is a method including depositing a first dielectric layer over a molding compound and a chip and patterning a first opening in the first dielectric layer to expose a contact of the chip. A first metallization layer is deposited over the first dielectric layer and in the first opening, where a portion of the first metallization layer in the first opening has a flat top. A second dielectric layer is deposited over the first metallization layer and the first dielectric layer. A second metallization layer is deposited in a second opening in the second dielectric layer, where the second metallization layer does not have a flat top within the second opening.Type: GrantFiled: July 29, 2019Date of Patent: August 11, 2020Assignee: Taiwan Semiconductor Manufacturing CompanyInventors: Wan-Ting Shih, Nai-Wei Liu, Jing-Cheng Lin, Cheng-Lin Huang
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Publication number: 20200220593Abstract: A communication system and a codec method based on deep learning and known channel state information (CSI) are provided. The communication system includes: a first electronic apparatus including a known first link CSI and a CSI encoder having a deep learning function; and a second electronic apparatus including a known second link CSI and a CSI decoder having a deep learning function. The first and second link CSIs have a correlation or a similarity. The CSI encoder of the first electronic apparatus encodes or compresses the first link CSI into the first codeword, and feeds the first codeword back to the second electronic apparatus via a feedback link. The CSI decoder of the second electronic apparatus encodes or compresses the second link CSI into a second codeword, and decodes or restores the first link CSI of the first electronic apparatus based on the first codeword and the second codeword.Type: ApplicationFiled: March 15, 2019Publication date: July 9, 2020Inventors: Chao-Kai Wen, Wan-Ting Shih, Ren-Jr Chen
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Publication number: 20190355684Abstract: An embodiment is a method including depositing a first dielectric layer over a molding compound and a chip and patterning a first opening in the first dielectric layer to expose a contact of the chip. A first metallization layer is deposited over the first dielectric layer and in the first opening, where a portion of the first metallization layer in the first opening has a flat top. A second dielectric layer is deposited over the first metallization layer and the first dielectric layer. A second metallization layer is deposited in a second opening in the second dielectric layer, where the second metallization layer does not have a flat top within the second opening.Type: ApplicationFiled: July 29, 2019Publication date: November 21, 2019Inventors: Wan-Ting Shih, Nai-Wei Liu, Jing-Cheng Lin, Cheng-Lin Huang
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Patent number: 10366960Abstract: An embodiment is a structure including a molding compound laterally encapsulating a chip with a contact pad. A first dielectric layer is formed overlying the molding compound. A first metallization layer is formed overlying the first dielectric layer, in which the first metallization layer extends through the first dielectric layer to contact the contact pad. A second dielectric layer is formed overlying the first metallization layer and the first dielectric layer. A second metallization layer is formed overlying the second dielectric layer and extends through the second dielectric layer to contact the first metallization layer.Type: GrantFiled: October 6, 2017Date of Patent: July 30, 2019Assignee: Taiwan Semiconductor Manufacturing CompanyInventors: Wan-Ting Shih, Nai-Wei Liu, Jing-Cheng Lin, Cheng-Lin Huang
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Publication number: 20180233441Abstract: A method of forming a PoP device comprises placing an adhesive layer on a carrier substrate, coupling a plurality of chip packages to the adhesive layer on the carrier substrate, placing a bonding layer on the chip packages, and coupling a plurality of chips to the bonding layer on the chip packages. The method further comprises injecting a molding compound to encapsulate the chip packages and the chips on the carrier substrate, grinding the molding compound to expose a plurality of connecting elements of the chips and a plurality of second connecting elements of the chip packages, forming a redistribution layer (RDL) on the molding compound and the exposed connecting elements and second connecting elements, forming a ball grid array (BGA) on the RDL, and de-bonding the carrier substrate.Type: ApplicationFiled: April 13, 2018Publication date: August 16, 2018Inventors: Chin-Chuan Chang, Jing-Cheng Lin, Nai-Wei Liu, Wan-Ting Shih
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Patent number: 9953907Abstract: A method of forming a PoP device comprises placing an adhesive layer on a carrier substrate, coupling a plurality of chip packages to the adhesive layer on the carrier substrate, placing a bonding layer on the chip packages, and coupling a plurality of chips to the bonding layer on the chip packages. The method further comprises injecting a molding compound to encapsulate the chip packages and the chips on the carrier substrate, grinding the molding compound to expose a plurality of connecting elements of the chips and a plurality of second connecting elements of the chip packages, forming a redistribution layer (RDL) on the molding compound and the exposed connecting elements and second connecting elements, forming a ball grid array (BGA) on the RDL, and de-bonding the carrier substrate.Type: GrantFiled: January 29, 2013Date of Patent: April 24, 2018Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chin-Chuan Chang, Jing-Cheng Lin, Nai-Wei Liu, Wan-Ting Shih
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Publication number: 20180033747Abstract: An embodiment is a structure including a molding compound laterally encapsulating a chip with a contact pad. A first dielectric layer is formed overlying the molding compound. A first metallization layer is formed overlying the first dielectric layer, in which the first metallization layer extends through the first dielectric layer to contact the contact pad. A second dielectric layer is formed overlying the first metallization layer and the first dielectric layer. A second metallization layer is formed overlying the second dielectric layer and extends through the second dielectric layer to contact the first metallization layer.Type: ApplicationFiled: October 6, 2017Publication date: February 1, 2018Inventors: Wan-Ting Shih, Nai-Wei Liu, Jing-Cheng Lin, Cheng-Lin Huang
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Patent number: 9824989Abstract: An embodiment is a package including a molding compound laterally encapsulating a chip with a contact pad. A first dielectric layer is formed overlying the molding compound and the chip and has a first opening exposing the contact pad. A first metallization layer is formed overlying the first dielectric layer, in which the first metallization layer fills the first opening. A second dielectric layer is formed overlying the first metallization layer and the first dielectric layer and has a second opening over the first opening. A second metallization layer is formed overlying the second dielectric layer and formed in the second opening.Type: GrantFiled: July 2, 2014Date of Patent: November 21, 2017Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Wan-Ting Shih, Nai-Wei Liu, Jing-Cheng Lin, Cheng-Lin Huang
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Patent number: 9312148Abstract: A method of packaging a semiconductor device includes forming an insulating layer over a semiconductor device, wherein the semiconductor device has a contact pad, and a thickness of the contact pad is greater than a thickness of the insulating layer. The method further includes forming a molding compound to cover the semiconductor device and a space between the semiconductor device and a neighboring semiconductor device, wherein both semiconductor devices are on a carrier wafer. The method further includes planarizing a surface of the semiconductor device by removing the molding compound and the insulating layer over the contact pad.Type: GrantFiled: March 16, 2015Date of Patent: April 12, 2016Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Jing-Cheng Lin, Jui-Pin Hung, Nai-Wei Liu, Yi-Chao Mao, Wan-Ting Shih, Tsan-Hua Tung
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Publication number: 20160005702Abstract: An embodiment is a package including a molding compound laterally encapsulating a chip with a contact pad. A first dielectric layer is formed overlying the molding compound and the chip and has a first opening exposing the contact pad. A first metallization layer is formed overlying the first dielectric layer, in which the first metallization layer fills the first opening. A second dielectric layer is formed overlying the first metallization layer and the first dielectric layer and has a second opening over the first opening. A second metallization layer is formed overlying the second dielectric layer and formed in the second opening.Type: ApplicationFiled: July 2, 2014Publication date: January 7, 2016Inventors: Wan-Ting Shih, Nai-Wei Liu, Jing-Cheng Lin, Cheng-Lin Huang
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Publication number: 20150187605Abstract: A method of packaging a semiconductor device includes forming an insulating layer over a semiconductor device, wherein the semiconductor device has a contact pad, and a thickness of the contact pad is greater than a thickness of the insulating layer. The method further includes forming a molding compound to cover the semiconductor device and a space between the semiconductor device and a neighboring semiconductor device, wherein both semiconductor devices are on a carrier wafer. The method further includes planarizing a surface of the semiconductor device by removing the molding compound and the insulating layer over the contact pad.Type: ApplicationFiled: March 16, 2015Publication date: July 2, 2015Inventors: Jing-Cheng LIN, Jui-Pin HUNG, Nai-Wei LIU, Yi-Chao MAO, Wan-Ting SHIH, Tsan-Hua TUNG
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Patent number: 9000584Abstract: The mechanisms of forming a molding compound on a semiconductor device substrate to enable fan-out structures in wafer-level packaging (WLP) are provided. The mechanisms involve covering portions of surfaces of an insulating layer surrounding a contact pad. The mechanisms improve reliability of the package and process control of the packaging process. The mechanisms also reduce the risk of interfacial delamination, and excessive outgassing of the insulating layer during subsequent processing. The mechanisms further improve planarization end-point. By utilizing a protective layer between the contact pad and the insulating layer, copper out-diffusion can be reduced and the adhesion between the contact pad and the insulating layer may also be improved.Type: GrantFiled: December 28, 2011Date of Patent: April 7, 2015Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Jing-Cheng Lin, Jui-Pin Hung, Nai-Wei Liu, Yi-Chao Mao, Wan-Ting Shih, Tsan-Hua Tung
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Publication number: 20140210080Abstract: A method of forming a PoP device comprises placing an adhesive layer on a carrier substrate, coupling a plurality of chip packages to the adhesive layer on the carrier substrate, placing a bonding layer on the chip packages, and coupling a plurality of chips to the bonding layer on the chip packages. The method further comprises injecting a molding compound to encapsulate the chip packages and the chips on the carrier substrate, grinding the molding compound to expose a plurality of connecting elements of the chips and a plurality of second connecting elements of the chip packages, forming a redistribution layer (RDL) on the molding compound and the exposed connecting elements and second connecting elements, forming a ball grid array (BGA) on the RDL, and de-bonding the carrier substrate.Type: ApplicationFiled: January 29, 2013Publication date: July 31, 2014Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chin-Chuan Chang, Jing-Cheng Lin, Nai-Wei Liu, Wan-Ting Shih
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Publication number: 20130168848Abstract: The mechanisms of forming a molding compound on a semiconductor device substrate to enable fan-out structures in wafer-level packaging (WLP) are provided. The mechanisms involve covering portions of surfaces of an insulating layer surrounding a contact pad. The mechanisms improve reliability of the package and process control of the packaging process. The mechanisms also reduce the risk of interfacial delamination, and excessive outgassing of the insulating layer during subsequent processing. The mechanisms further improve planarization end-point. By utilizing a protective layer between the contact pad and the insulating layer, copper out-diffusion can be reduced and the adhesion between the contact pad and the insulating layer may also be improved.Type: ApplicationFiled: December 28, 2011Publication date: July 4, 2013Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Jing-Cheng LIN, Jui-Pin HUNG, Nai-Wei LIU, Yi-Chao MAO, Wan-Ting SHIH, Tsan-Hua TUNG