Abstract: SRAM structures are provided. An SRAM structure includes a substrate, a P-type well region over the substrate, an N-type well region over the substrate, a PMOS transistor in the N-type well region, an NMOS transistor in the P-type well region, an isolation region over the boundary between the P-type well region and the N-type well region, and a dielectric structure formed in the isolation region and extending from the isolation region to the boundary between the P-type well region and the N-type well region. The depth of the dielectric structure is greater than that of the isolation region. The PMOS transistor is separated from the NMOS transistor by the isolation region.

Abstract: SRAM structures are provided. An SRAM structure includes a substrate, a P-type well region over the substrate, an N-type well region over the substrate, a PMOS transistor in the N-type well region, an NMOS transistor in the P-type well region, an isolation region over the boundary between the P-type well region and the N-type well region, and a dielectric structure formed in the isolation region and extending from the isolation region to the boundary between the P-type well region and the N-type well region. The depth of the dielectric structure is greater than that of the isolation region. The PMOS transistor is separated from the NMOS transistor by the isolation region.

Abstract: The present disclosure describes a method of fabricating a semiconductor structure that includes forming a gate structure over a substrate, forming an interlayer dielectric structure surrounding the gate structures, and forming a first opening in the gate structure and the interlayer dielectric structure. The first opening has a first portion in the gate structure and a second portion in the interlayer dielectric structure, in which the first portion has a width larger than the second portion. The method further includes depositing a dielectric layer in the first opening and forming a second opening over the first opening. The first portion of the opening remains open and the second portion of the opening is filled after depositing the dielectric layer. The second opening in the gate structure has a depth larger than the first opening in the gate structure.

Abstract: The present disclosure describes a method of fabricating a semiconductor structure that includes forming a gate structure over a substrate, forming an interlayer dielectric structure surrounding the gate structures, and forming a first opening in the gate structure and the interlayer dielectric structure. The first opening has a first portion in the gate structure and a second portion in the interlayer dielectric structure, in which the first portion has a width larger than the second portion. The method further includes depositing a dielectric layer in the first opening and forming a second opening over the first opening. The first portion of the opening remains open and the second portion of the opening is filled after depositing the dielectric layer. The second opening in the gate structure has a depth larger than the first opening in the gate structure.

Abstract: The present disclosure describes a method of fabricating a semiconductor structure that includes forming a gate structure over a substrate, forming an interlayer dielectric structure surrounding the gate structures, and forming a first opening in the gate structure and the interlayer dielectric structure. The first opening has a first portion in the gate structure and a second portion in the interlayer dielectric structure, in which the first portion has a width larger than the second portion. The method further includes depositing a dielectric layer in the first opening and forming a second opening over the first opening. The first portion of the opening remains open and the second portion of the opening is filled after depositing the dielectric layer. The second opening in the gate structure has a depth larger than the first opening in the gate structure.

Abstract: SRAM structures are provided. An SRAM structure includes a substrate, a P-type well region over the substrate, an N-type well region over the substrate, a PMOS transistor in the N-type well region, an NMOS transistor in the P-type well region, an isolation region over the boundary between the P-type well region and the N-type well region, and a dielectric structure formed in the isolation region and extending from the isolation region to the boundary between the P-type well region and the N-type well region. The depth of the dielectric structure is greater than that of the isolation region. The PMOS transistor is separated from the NMOS transistor by the isolation region.