Patents by Inventor Wan-Yu Chiang
Wan-Yu Chiang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240145327Abstract: A semiconductor device includes a substrate, an interconnect structure, and conductive vias. The substrate has a first side, a second side and a sidewall connecting the first side and the second side, wherein the sidewall includes a first planar sidewall of a first portion of the substrate, a second planar sidewall of a second portion of the substrate and a curved sidewall of a third portion of the substrate, where the first planar sidewall is connected to the second planar sidewall through the curved sidewall. The interconnect structure is located on the first side of the substrate, where a sidewall of the interconnect structure is offset from the second planar sidewall. The conductive vias are located on the interconnect structure, where the interconnect structure is located between the conductive vias and the substrate.Type: ApplicationFiled: December 27, 2023Publication date: May 2, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chang-Jung Hsueh, Cheng-Nan Lin, Wan-Yu Chiang, Wei-Hung Lin, Ching-Wen Hsiao, Ming-Da Cheng
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Publication number: 20240128219Abstract: A semiconductor die including mechanical-stress-resistant bump structures is provided. The semiconductor die includes dielectric material layers embedding metal interconnect structures, a connection pad-and-via structure, and a bump structure including a bump via portion and a bonding bump portion. The entirety of a bottom surface of the bump via portion is located within an area of a horizontal top surface of a pad portion of the connection pad-and-via structure.Type: ApplicationFiled: December 6, 2023Publication date: April 18, 2024Inventors: Hui-Min Huang, Wei-Hung Lin, Kai Jun Zhan, Chang-Jung Hsueh, Wan-Yu Chiang, Ming-Da Cheng
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Publication number: 20240088119Abstract: Provided are a package structure and a method of forming the same. The method includes providing a first package having a plurality of first dies and a plurality of second dies therein; performing a first sawing process to cut the first package into a plurality of second packages, wherein one of the plurality of second packages comprises three first dies and one second die; and performing a second sawing process to remove the second die of the one of the plurality of second packages, so that a cut second package is formed into a polygonal structure with the number of nodes greater than or equal to 5.Type: ApplicationFiled: November 21, 2023Publication date: March 14, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Wei-Hung Lin, Hui-Min Huang, Chang-Jung Hsueh, Wan-Yu Chiang, Ming-Da Cheng, Mirng-Ji Lii
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Patent number: 11901256Abstract: A semiconductor device includes a substrate, an interconnect structure, and conductive vias. The substrate has a first side, a second side and a sidewall connecting the first side and the second side, wherein the sidewall includes a first planar sidewall of a first portion of the substrate, a second planar sidewall of a second portion of the substrate and a curved sidewall of a third portion of the substrate, where the first planar sidewall is connected to the second planar sidewall through the curved sidewall. The interconnect structure is located on the first side of the substrate, where a sidewall of the interconnect structure is offset from the second planar sidewall. The conductive vias are located on the interconnect structure, where the interconnect structure is located between the conductive vias and the substrate.Type: GrantFiled: August 31, 2021Date of Patent: February 13, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chang-Jung Hsueh, Cheng-Nan Lin, Wan-Yu Chiang, Wei-Hung Lin, Ching-Wen Hsiao, Ming-Da Cheng
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Publication number: 20240038752Abstract: Provided are a package structure and a method of forming the same. The method includes providing a first package having a plurality of first dies and a plurality of second dies therein; performing a first sawing process to cut the first package into a plurality of second packages, wherein one of the plurality of second packages comprises three first dies and one second die; and performing a second sawing process to remove the second die of the one of the plurality of second packages, so that a cut second package is formed into a polygonal structure with the number of nodes greater than or equal to 5.Type: ApplicationFiled: October 5, 2023Publication date: February 1, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Wei-Hung Lin, Hui-Min Huang, Chang-Jung Hsueh, Wan-Yu Chiang, Ming-Da Cheng, Mirng-Ji Lii
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Patent number: 11887955Abstract: A semiconductor die including mechanical-stress-resistant bump structures is provided. The semiconductor die includes dielectric material layers embedding metal interconnect structures, a connection pad-and-via structure, and a bump structure including a bump via portion and a bonding bump portion. The entirety of a bottom surface of the bump via portion is located within an area of a horizontal top surface of a pad portion of the connection pad-and-via structure.Type: GrantFiled: August 26, 2021Date of Patent: January 30, 2024Assignee: Taiwan Semiconductor Manufacturing Company LimitedInventors: Hui-Min Huang, Ming-Da Cheng, Chang-Jung Hsueh, Wei-Hung Lin, Kai Jun Zhan, Wan-Yu Chiang
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Patent number: 11855058Abstract: Provided are a package structure and a method of forming the same. The method includes providing a first package having a plurality of first dies and a plurality of second dies therein; performing a first sawing process to cut the first package into a plurality of second packages, wherein one of the plurality of second packages comprises three first dies and one second die; and performing a second sawing process to remove the second die of the one of the plurality of second packages, so that a cut second package is formed into a polygonal structure with the number of nodes greater than or equal to 5.Type: GrantFiled: August 30, 2021Date of Patent: December 26, 2023Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Wei-Hung Lin, Hui-Min Huang, Chang-Jung Hsueh, Wan-Yu Chiang, Ming-Da Cheng, Mirng-Ji Lii
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Publication number: 20230062370Abstract: Provided are a package structure and a method of forming the same. The method includes providing a first package having a plurality of first dies and a plurality of second dies therein; performing a first sawing process to cut the first package into a plurality of second packages, wherein one of the plurality of second packages comprises three first dies and one second die; and performing a second sawing process to remove the second die of the one of the plurality of second packages, so that a cut second package is formed into a polygonal structure with the number of nodes greater than or equal to 5.Type: ApplicationFiled: August 30, 2021Publication date: March 2, 2023Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Wei-Hung Lin, Hui-Min Huang, Chang-Jung Hsueh, Wan-Yu Chiang, Ming-Da Cheng, Mirng-Ji Lii
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Publication number: 20230068485Abstract: A semiconductor device includes a substrate, an interconnect structure, and conductive vias. The substrate has a first side, a second side and a sidewall connecting the first side and the second side, wherein the sidewall includes a first planar sidewall of a first portion of the substrate, a second planar sidewall of a second portion of the substrate and a curved sidewall of a third portion of the substrate, where the first planar sidewall is connected to the second planar sidewall through the curved sidewall. The interconnect structure is located on the first side of the substrate, where a sidewall of the interconnect structure is offset from the second planar sidewall. The conductive vias are located on the interconnect structure, where the interconnect structure is located between the conductive vias and the substrate.Type: ApplicationFiled: August 31, 2021Publication date: March 2, 2023Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chang-Jung Hsueh, Cheng-Nan Lin, Wan-Yu Chiang, Wei-Hung Lin, Ching-Wen Hsiao, Ming-Da Cheng
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Publication number: 20230065797Abstract: A semiconductor die including mechanical-stress-resistant bump structures is provided. The semiconductor die includes dielectric material layers embedding metal interconnect structures, a connection pad-and-via structure, and a bump structure including a bump via portion and a bonding bump portion. The entirety of a bottom surface of the bump via portion is located within an area of a horizontal top surface of a pad portion of the connection pad-and-via structure.Type: ApplicationFiled: August 26, 2021Publication date: March 2, 2023Inventors: Hui-Min HUANG, Ming-Da CHENG, Chang-Jung HSUEH, Wei-Hung LIN, Kai Jun ZHAN, Wan-Yu CHIANG
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Publication number: 20230014210Abstract: An adjustable wrench is disclosed. The adjustable wrench is used for an assembly part. The adjustable wrench includes a frame, an adjustable member, and an engaging element. The adjustable member is adjacent to the frame to form a space between an inner side of the frame, wherein the adjustable member further has a rack. The engaging element is adjacent to the adjustable member and has an engaging portion that meshes with the rack such that, after the adjustable member slides, a position of the engaging portion meshed with the rack is changed so as to change the size of the space; thus, the space can be adjusted to match assembly parts of different specifications.Type: ApplicationFiled: October 12, 2021Publication date: January 19, 2023Inventors: Chien-Chou Liao, Chien-Wei Huang, Wan-Yu Chiang
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Publication number: 20170373453Abstract: A crimping tool used for crimping terminals and wires includes a driving mechanism, a crimping mechanism and a plurality of adjustable elements. The crimping mechanism includes a compensation element and a crimping block, wherein the compensation element includes an accommodating space, an accommodating groove and a plurality of through holes. The accommodating groove and the through holes communicate with the accommodating space. The accommodating groove is used for accommodating the terminal. The crimping block is connected to the driving mechanism and movably disposed in the accommodating space. Each of the adjustable elements is movably disposed in each of the through holes such that it can be moved into the accommodating space to be against the crimping block such that the convex teeth of the crimping block are aligned with a plurality of pins on the terminal.Type: ApplicationFiled: August 15, 2016Publication date: December 28, 2017Inventors: Chien-Chou Liao, Wan-Yu Chiang
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Publication number: 20150295391Abstract: A stripper is disclosed. The stripper includes a pair of plier bodies and at least one pair of blades. The two plier bodies are pivotally connected to each other. Each plier body includes a cutting part and a stripping part, wherein the cutting parts of the pair of plier bodies are used for cutting a wire, and one side of each of the stripping parts includes at least one plier body notch. The plier body notches are used for forming an opening for containing the wire when the pair of plier bodies are clamped. The at least one pair of blades are respectively removably connected to the stripping parts of each of the plier bodies, and the two blades are used for removing at least one covering layer of the wire.Type: ApplicationFiled: June 9, 2014Publication date: October 15, 2015Inventors: Chien-Chou Liao, Wan-Yu Chiang
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Patent number: D760050Type: GrantFiled: May 13, 2014Date of Patent: June 28, 2016Assignee: Hanlong Industrial Co., Ltd.Inventors: Chien-Chou Liao, Wan-Yu Chiang
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Patent number: D847599Type: GrantFiled: January 8, 2018Date of Patent: May 7, 2019Assignee: Hanlong Industrial Co., Ltd.Inventor: Wan-Yu Chiang
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Patent number: D931699Type: GrantFiled: December 4, 2019Date of Patent: September 28, 2021Assignee: Hanlong Industrial Co., Ltd.Inventor: Wan-Yu Chiang
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Patent number: D950341Type: GrantFiled: September 15, 2020Date of Patent: May 3, 2022Assignee: Hanlong Industrial Co., Ltd.Inventor: Wan-Yu Chiang
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Patent number: D983634Type: GrantFiled: January 4, 2021Date of Patent: April 18, 2023Assignee: Hanlong Industrial Co., Ltd.Inventor: Wan-Yu Chiang