Patents by Inventor Wan Yu KAI

Wan Yu KAI has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12268021
    Abstract: An apparatus includes a drain and a source on opposing sides of an epitaxial layer, a plurality of gates formed in the epitaxial layer, a source contact connected to the source, a gate contact connected to the plurality of gates, a gate-source electrostatic discharge (ESD) diode connected between the gate contact and the source contact, and a breakdown voltage enhancement and leakage prevention structure formed underneath the gate-source ESD diode structure.
    Type: Grant
    Filed: June 4, 2024
    Date of Patent: April 1, 2025
    Assignee: Diodes Incorporated
    Inventors: Wan-Yu Kai, Chia-Wei Hu, Ta-Chuan Kuo
  • Patent number: 12256562
    Abstract: A method includes growing an epitaxial layer over a substrate, forming a plurality of gates in the epitaxial layer, forming a source in the epitaxial layer, forming a breakdown voltage enhancement and leakage prevention structure comprising a body ring structure in the epitaxial layer, forming a gate-source Electrostatic Discharge (ESD) diode structure over the epitaxial layer, forming a source contact connected to the source and a first terminal of the gate-source ESD diode structure, forming a gate contact connected to the plurality of gates and a second terminal of the gate-source ESD diode structure.
    Type: Grant
    Filed: June 20, 2024
    Date of Patent: March 18, 2025
    Assignee: Diodes Incorporated
    Inventors: Wan-Yu Kai, Chia-Wei Hu, Ta-Chuan Kuo
  • Patent number: 12224311
    Abstract: An apparatus includes a drain and a source on opposing sides of an epitaxial layer, a plurality of gates formed in the epitaxial layer, a source contact connected to the source, a gate contact connected to the plurality of gates, a drain contact on opposing sides of the epitaxial layer of the source contact, a gate-source electrostatic discharge (ESD) diode connected between the gate contact and the source contact, and a breakdown voltage enhancement and leakage prevention structure formed underneath the gate-source ESD diode structure, wherein the breakdown voltage enhancement and leakage prevention structure comprises a body ring structure.
    Type: Grant
    Filed: June 18, 2024
    Date of Patent: February 11, 2025
    Assignee: Diodes Incorporated
    Inventors: Wan-Yu Kai, Chia-Wei Hu, Ta-Chuan Kuo
  • Publication number: 20250048702
    Abstract: A semiconductor device includes a substrate, a gate structure over the substrate, a dielectric layer over the substrate and surrounding the gate structure, a contact extending in the dielectric layer to the substrate, a protection layer surrounding a portion of the contact embedded in the substrate, an etch stop layer between the dielectric layer and the substrate extending from the gate structure to the contact, in which a top surface of the protection layer is lower than a top surface of the etch stop layer; and a metal alloy structure at a bottom of the contact.
    Type: Application
    Filed: October 21, 2024
    Publication date: February 6, 2025
    Inventor: Wan Yu KAI
  • Patent number: 12170311
    Abstract: A method includes growing an epitaxial layer over a substrate, forming a plurality of gates in the epitaxial layer, forming a breakdown voltage enhancement and leakage prevention structure in the epitaxial layer comprising a body ring structure, forming a source and a body region in the epitaxial layer, forming an interlayer dielectric layer over the epitaxial layer, forming a gate-source Electrostatic Discharge (ESD) diode structure in the interlayer dielectric layer, forming a source contact connected to the source, and a first terminal of the gate-source ESD diode structure, forming a gate contact connected to the plurality of gates and a second terminal of the gate-source ESD diode structure, and forming a drain contact underneath the substrate.
    Type: Grant
    Filed: July 2, 2024
    Date of Patent: December 17, 2024
    Assignee: Diodes Incorporated
    Inventors: Wan-Yu Kai, Chia-Wei Hu, Ta-Chuan Kuo
  • Patent number: 12154954
    Abstract: A manufacturing method of a semiconductor device includes forming a contact opening in a wafer. The wafer includes a substrate, a gate structure over the substrate and a dielectric layer over the substrate and surrounding the gate structure, and the contact opening passes through the dielectric layer and exposes the substrate. A recess is formed in the substrate such that the recess is connected to the contact opening. An oxidation process is performed to convert a portion of the substrate exposed in the recess to form a protection layer lining a sidewall and a bottom surface of the recess. The protection layer is etched back to remove a first portion of the protection layer in contact with the bottom surface of the recess of the substrate. A metal alloy structure is formed at the bottom surface of the recess of the substrate.
    Type: Grant
    Filed: October 30, 2023
    Date of Patent: November 26, 2024
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventor: Wan Yu Kai
  • Patent number: 12154942
    Abstract: A method includes growing an epitaxial layer over a substrate, forming a plurality of gates in the epitaxial layer, forming a breakdown voltage enhancement and leakage prevention structure in the epitaxial layer, comprising a body ring structure, forming a source in the epitaxial layer and a gate-source Electrostatic Discharge (ESD) diode structure over the epitaxial layer, forming a source contact connected to the source and a first terminal of the gate-source ESD diode structure, forming a gate contact connected to the plurality of gates and a second terminal of the gate-source ESD diode structure, and forming a drain contact on the opposing side of the epitaxial layer from the source contact.
    Type: Grant
    Filed: June 18, 2024
    Date of Patent: November 26, 2024
    Assignee: Diodes Incorporated
    Inventors: Wan-Yu Kai, Chia-Wei Hu, Ta-Chuan Kuo
  • Patent number: 12154941
    Abstract: An apparatus includes a drain and a source on opposing sides of an epitaxial layer, a plurality of gates formed in the epitaxial layer, a source contact connected to the source, a gate contact connected to the plurality of gates, a gate-source electrostatic discharge (ESD) diode connected between the gate contact and the source contact, and a breakdown voltage enhancement and leakage prevention structure formed underneath the gate-source ESD diode structure.
    Type: Grant
    Filed: January 18, 2024
    Date of Patent: November 26, 2024
    Assignee: Diodes Incorporated
    Inventors: Wan-Yu Kai, Chia-Wei Hu, Ta-Chuan Kuo
  • Patent number: 11948982
    Abstract: A manufacturing method of a semiconductor device includes forming a contact opening in a wafer. The wafer includes a substrate, a gate structure over the substrate and a dielectric layer over the substrate and surrounding the gate structure, and the contact opening passes through the dielectric layer and exposes the substrate. A recess is formed in the substrate such that the recess is connected to the contact opening. An oxidation process is performed to convert a portion of the substrate exposed in the recess to form a protection layer lining a sidewall and a bottom surface of the recess. The protection layer is etched back to remove a first portion of the protection layer in contact with the bottom surface of the recess of the substrate. A metal alloy structure is formed at the bottom surface of the recess of the substrate.
    Type: Grant
    Filed: November 24, 2021
    Date of Patent: April 2, 2024
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventor: Wan Yu Kai
  • Publication number: 20240063273
    Abstract: A manufacturing method of a semiconductor device includes forming a contact opening in a wafer. The wafer includes a substrate, a gate structure over the substrate and a dielectric layer over the substrate and surrounding the gate structure, and the contact opening passes through the dielectric layer and exposes the substrate. A recess is formed in the substrate such that the recess is connected to the contact opening. An oxidation process is performed to convert a portion of the substrate exposed in the recess to form a protection layer lining a sidewall and a bottom surface of the recess. The protection layer is etched back to remove a first portion of the protection layer in contact with the bottom surface of the recess of the substrate. A metal alloy structure is formed at the bottom surface of the recess of the substrate.
    Type: Application
    Filed: October 30, 2023
    Publication date: February 22, 2024
    Inventor: Wan Yu KAI