Patents by Inventor Wan-Yu Lo
Wan-Yu Lo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11929331Abstract: The present disclosure provides a routing structure. The routing structure includes a substrate having a boundary and a first conductive trace configured to be coupled to a first conductive pad disposed within the boundary of the substrate. The first conductive trace is inclined with respect to the boundary of the substrate.Type: GrantFiled: December 19, 2022Date of Patent: March 12, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Chin-Shen Lin, Wan-Yu Lo, Meng-Xiang Lee, Hao-Tien Kan, Kuo-Nan Yang, Chung-Hsing Wang
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Publication number: 20230367945Abstract: The present disclosure provides methods and a non-transitory computer readable media for resistance and capacitance (RC) extraction. The method comprises: receiving an electronic layout; selecting a two-dimensional (2D) conductive element from the electronic layout, wherein an aspect ratio of the 2D conductive element is lower than a predetermined threshold; partitioning the 2D conductive element into a plurality of polygons; determining a parasitic capacitance value for each polygon; determining multiple parasitic resistance values for each polygon; determining a total capacitance value of the 2D conductive element based on the parasitic capacitance value for each polygon; and determining a total resistance value of the 2D conductive element based on the multiple parasitic resistance values for each polygon.Type: ApplicationFiled: May 12, 2022Publication date: November 16, 2023Inventors: CHIN-SHEN LIN, WAN-YU LO, KUO-NAN YANG, CHUNG-HSING WANG
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Publication number: 20230260906Abstract: Semiconductor devices are provided. A semiconductor device includes a semiconductor substrate, a power switch, a first power mesh and a second power mesh. The power switch is formed over the front surface of the semiconductor substrate. The first power mesh is formed over the power switch and is directly connected to the first terminal of the power switch. The second power mesh is formed over the back surface of the semiconductor substrate and is directly connected to the second terminal of the power switch.Type: ApplicationFiled: January 27, 2022Publication date: August 17, 2023Inventors: Wan-Yu LO, Chin-Shen LIN, Chi-Yu LU, Kuo-Nan YANG, Chih-Liang CHEN, Chung-Hsing WANG
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Publication number: 20230252219Abstract: A method of forming a semiconductor device including: providing a first circuit cell including a first pin cell; forming a connecting path originated from the first pin cell of the first circuit cell; performing an Electromigration (EM) checking process with a first parasitic capacitance of the first pin cell and a second parasitic capacitance of the connecting path by loading a loading capacitance file to determine whether the loading capacitance of the first pin cell is larger than a first predetermined capacitance; and substituting a second pin cell for the first pin cell when the loading capacitance of the first pin cell is larger than the first predetermined capacitance, wherein the second pin cell is different from the first pin cell.Type: ApplicationFiled: April 19, 2023Publication date: August 10, 2023Inventors: KUO-NAN YANG, WAN-YU LO, CHUNG-HSING WANG, HIRANMAY BISWAS
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Patent number: 11669669Abstract: A method for manufacturing a semiconductor device is provided. The method comprises determining a dimensional quantity of a layout pattern having an angle relative to grid lines of a minimum grid. The minimum grid may be defined by a first quantity associated with a first direction and a second quantity associated with a second direction perpendicular to the first direction. The determination of the dimensional quantity of the layout pattern is based on the first quantity, the second quantity and the angle of the layout pattern relative to the grid lines of the minimum grid.Type: GrantFiled: July 30, 2020Date of Patent: June 6, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Chin-Shen Lin, Wan-Yu Lo, Shao-Huan Wang, Kuo-Nan Yang, Chung-Hsing Wang, Sheng-Hsiung Chen, Huang-Yu Chen
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Patent number: 11657199Abstract: Methods for analyzing electromigration (EM) in an integrated circuit (IC) are provided. A layout of the IC is obtained. A metal segment is selected from the layout according to a current simulation result of the IC. Two first vias are formed over and in contact with the metal segment in the layout. EM rule is kept on the metal segment when a distance between the two first vias is greater than a threshold distance. The EM rule is relaxed on the metal segment when the distance between the two first vias is less than or equal to the threshold distance.Type: GrantFiled: July 21, 2022Date of Patent: May 23, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chin-Shen Lin, Ming-Hsien Lin, Wan-Yu Lo, Meng-Xiang Lee
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Publication number: 20230154849Abstract: Various layouts for conductive interconnects in the conductor layers in an integrated circuit are disclosed. Some or all of the conductive interconnects are included in a power delivery system. In general, the conductive interconnects in a first conductor layer are arranged according to an orthogonal layout and the conductive interconnects in a second conductor layer are arranged according to a non-orthogonal layout. Conductive stripes in a transition conductor layer positioned between the first and the second conductor layers electrically connect the conductive interconnects in the first conductor layer to the conductive interconnects in the second conductor layer.Type: ApplicationFiled: January 18, 2023Publication date: May 18, 2023Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Wan-Yu LO, Chung-Hsing WANG, Chin-Shen LIN, Kuo-Nan YANG, Meng-Xiang LEE, Hao-Tien KAN, Jhih-Hong YE
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Patent number: 11651136Abstract: A method of forming a semiconductor device includes: providing a first circuit having a plurality of circuit cells; analyzing a loading capacitance on a first pin cell connecting a first circuit cell and a second circuit cell in the plurality of circuit cells to determine if the loading capacitance of the first pin cell is larger than a first predetermined capacitance; replacing the first pin cell by a second pin cell for generating a second circuit when the loading capacitance is larger than the first predetermined capacitance, wherein the second pin cell is different from the first pin cell; and generating the semiconductor device according to the second circuit.Type: GrantFiled: January 5, 2022Date of Patent: May 16, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Kuo-Nan Yang, Wan-Yu Lo, Chung-Hsing Wang, Hiranmay Biswas
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Publication number: 20230121445Abstract: The present disclosure provides a routing structure. The routing structure includes a substrate having a boundary and a first conductive trace configured to be coupled to a first conductive pad disposed within the boundary of the substrate. The first conductive trace is inclined with respect to the boundary of the substrate.Type: ApplicationFiled: December 19, 2022Publication date: April 20, 2023Inventors: CHIN-SHEN LIN, WAN-YU LO, MENG-XIANG LEE, HAO-TIEN KAN, KUO-NAN YANG, CHUNG-HSING WANG
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Patent number: 11600568Abstract: Various layouts for conductive interconnects in the conductor layers in an integrated circuit are disclosed. Some or all of the conductive interconnects are included in a power delivery system. In general, the conductive interconnects in a first conductor layer are arranged according to an orthogonal layout and the conductive interconnects in a second conductor layer are arranged according to a non-orthogonal layout. Conductive stripes in a transition conductor layer positioned between the first and the second conductor layers electrically connect the conductive interconnects in the first conductor layer to the conductive interconnects in the second conductor layer.Type: GrantFiled: June 18, 2021Date of Patent: March 7, 2023Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Wan-Yu Lo, Chung-Hsing Wang, Chin-Shen Lin, Kuo-Nan Yang, Meng-Xiang Lee, Hao-Tien Kan, Jhih-Hong Ye
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Publication number: 20220406716Abstract: Various layouts for conductive interconnects in the conductor layers in an integrated circuit are disclosed. Some or all of the conductive interconnects are included in a power delivery system. In general, the conductive interconnects in a first conductor layer are arranged according to an orthogonal layout and the conductive interconnects in a second conductor layer are arranged according to a non-orthogonal layout. Conductive stripes in a transition conductor layer positioned between the first and the second conductor layers electrically connect the conductive interconnects in the first conductor layer to the conductive interconnects in the second conductor layer.Type: ApplicationFiled: June 18, 2021Publication date: December 22, 2022Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Wan-Yu LO, Chung-Hsing WANG, Chin-Shen LIN, Kuo-Nan YANG, Meng-Xiang LEE, Hao-Tien KAN, Jhih-Hong YE
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Patent number: 11532562Abstract: The present disclosure provides a routing structure. The routing structure includes a substrate having a first circuit region and a boundary surrounding the first circuit region. The routing structure also includes a first conductive trace coupled to a first conductive pad disposed in the first circuit region. The first conductive trace is inclined with respect to the boundary of the substrate. A method of forming a routing structure is also disclosed.Type: GrantFiled: June 24, 2020Date of Patent: December 20, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Chin-Shen Lin, Wan-Yu Lo, Meng-Xiang Lee, Hao-Tien Kan, Kuo-Nan Yang, Chung-Hsing Wang
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Publication number: 20220358271Abstract: Methods for analyzing electromigration (EM) in an integrated circuit (IC) are provided. A layout of the IC is obtained. A metal segment is selected from the layout according to a current simulation result of the IC. Two first vias are formed over and in contact with the metal segment in the layout. EM rule is kept on the metal segment when a distance between the two first vias is greater than a threshold distance. The EM rule is relaxed on the metal segment when the distance between the two first vias is less than or equal to the threshold distance.Type: ApplicationFiled: July 21, 2022Publication date: November 10, 2022Inventors: Chin-Shen LIN, Ming-Hsien LIN, Wan-Yu LO, Meng-Xiang LEE
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Patent number: 11455448Abstract: Methods for analyzing electromigration (EM) in an integrated circuit (IC) are provided. The layout of the IC is obtained. A metal segment is selected from the layout according to a current simulation result of the IC. EM rule is kept on the metal segment when a single via is formed over and in contact with the metal segment in the layout. The EM rule is relaxed on the metal segment when two first vias are formed over and in contact with the metal segment in the layout. The two first vias have the same current direction.Type: GrantFiled: March 23, 2021Date of Patent: September 27, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chin-Shen Lin, Ming-Hsien Lin, Wan-Yu Lo, Meng-Xiang Lee
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Publication number: 20220285263Abstract: A method of forming a semiconductor arrangement includes forming a first capacitor in a first voltage domain and forming a second capacitor in the first voltage domain. The first capacitor is connected in parallel with the second capacitor. A third capacitor and a fourth capacitor are formed in a second voltage domain. The third capacitor is connected in series with the fourth capacitor. The first capacitor and the second capacitor are connected in parallel with a supply terminal of the first voltage domain and a reference terminal of the first voltage domain. The fourth capacitor is connected to a supply terminal of the second voltage domain. The third capacitor is connected to a reference terminal of the second voltage domain.Type: ApplicationFiled: June 1, 2021Publication date: September 8, 2022Inventors: Wan-Yu Lo, Chung-Hsing Wang, Chin-Shen Lin, Kuo-Nan Yang, Hsiang-Ku Shen, Dian-Hau Chen
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Publication number: 20220129614Abstract: A method of forming a semiconductor device includes: providing a first circuit having a plurality of circuit cells; analyzing a loading capacitance on a first pin cell connecting a first circuit cell and a second circuit cell in the plurality of circuit cells to determine if the loading capacitance of the first pin cell is larger than a first predetermined capacitance; replacing the first pin cell by a second pin cell for generating a second circuit when the loading capacitance is larger than the first predetermined capacitance, wherein the second pin cell is different from the first pin cell; and generating the semiconductor device according to the second circuit.Type: ApplicationFiled: January 5, 2022Publication date: April 28, 2022Inventors: KUO-NAN YANG, WAN-YU LO, CHUNG-HSING WANG, HIRANMAY BISWAS
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Publication number: 20220035982Abstract: A method for manufacturing a semiconductor device is provided. The method comprises determining a dimensional quantity of a layout pattern having an angle relative to grid lines of a minimum grid. The minimum grid may be defined by a first quantity associated with a first direction and a second quantity associated with a second direction perpendicular to the first direction. The determination of the dimensional quantity of the layout pattern is based on the first quantity, the second quantity and the angle of the layout pattern relative to the grid lines of the minimum grid.Type: ApplicationFiled: July 30, 2020Publication date: February 3, 2022Inventors: CHIN-SHEN LIN, WAN-YU LO, SHAO-HUAN WANG, KUO-NAN YANG, CHUNG-HSING WANG, SHENG-HSIUNG CHEN, HUANG-YU CHEN
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Patent number: 11227093Abstract: A method of forming a semiconductor device includes: providing a first circuit having a plurality of circuit cells; analyzing a loading capacitance on a first pin cell connecting a first circuit cell and a second circuit cell in the plurality of circuit cells to determine if the loading capacitance of the first pin cell is larger than a first predetermined capacitance; replacing the first pin cell by a second pin cell for generating a second circuit when the loading capacitance is larger than the first predetermined capacitances, wherein the second pin cell is different from the first pin cell; and generating the semiconductor device according to the second circuit.Type: GrantFiled: January 25, 2021Date of Patent: January 18, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Kuo-Nan Yang, Wan-Yu Lo, Chung-Hsing Wang, Hiranmay Biswas
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Publication number: 20210407913Abstract: The present disclosure provides a routing structure. The routing structure includes a substrate having a first circuit region and a boundary surrounding the first circuit region. The routing structure also includes a first conductive trace coupled to a first conductive pad disposed in the first circuit region. The first conductive trace is inclined with respect to the boundary of the substrate. A method of forming a routing structure is also disclosed.Type: ApplicationFiled: June 24, 2020Publication date: December 30, 2021Inventors: CHIN-SHEN LIN, WAN-YU LO, MENG-XIANG LEE, HAO-TIEN KAN, KUO-NAN YANG, CHUNG-HSING WANG
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Publication number: 20210248297Abstract: In a method, cell placement is performed to place a plurality of cells into a region of an integrated circuit (IC). A thermal analysis is performed to determine whether the region of the IC is thermally stable at an operating condition. In response to a determination that the region of the IC is thermally unstable, at least one of a structure or the operating condition of the region of the IC is changed. After the thermal analysis, routing is performed to route a plurality of nets interconnecting the placed cells. At least one of the cell placement, the thermal analysis, the changing or the routing is executed by a processor.Type: ApplicationFiled: April 30, 2021Publication date: August 12, 2021Inventors: Wan-Yu LO, Kuo-Nan YANG, Chin-Shen LIN, Chung-Hsing WANG