Abstract: The present disclosure discloses a fabrication method for wafer-level packaging, comprising: forming a first photoresist on a first chip and a plurality of first openings at the first photoresist to expose a functional surface of the first chip, forming an under-bump metal layer on the functional surface exposed through the plurality of first openings, and removing the first photoresist; connecting a functional solder bump of a second chip to the under-bump metal layer on the first chip; forming a filling layer between the first chip, and the second chip; and forming a connecting member on the first chip, wherein a solder ball is disposed at a top surface of the connecting member, and an apex of the solder ball is higher than a top surface of the second chip.

Abstract: The present disclosure discloses a fabrication method for wafer-level packaging, comprising: forming a first photoresist on a first chip and a plurality of first openings at the first photoresist to expose a functional surface of the first chip, forming an under-bump metal layer on the functional surface exposed through the plurality of first openings, and removing the first photoresist; connecting a functional solder bump of a second chip to the under-bump metal layer on the first chip; forming a filling layer between the first chip and the second chip; and forming a connecting member on the first chip, wherein a solder ball is disposed at a top surface of the connecting member, and an apex of the solder ball is higher than a top surface of the second chip. The first chip and the second chip are disposed face-to-face, and the filling layer is formed between the first chip and the second chip. The solder ball is mounted on the connecting member.

Abstract: The present invention provides a semiconductor package structure, including: a chip, wherein bonding pads and a passivation layer are arranged on the surface of the chip, the passivation layer is provided with first openings for exposing the bonding pads, and a seed layer connected with the bonding pads and columnar salient points stacked on the seed layer are arranged on the bonding pads; lead frames, wherein each lead frame is provided with a plurality of discrete pins, and internal pins and external pins are respectively arranged on two opposite surfaces of the pins; the chip being flipped on the lead frames, and the columnar salient points being connected with the internal pins; a plastic package layer, wherein the plastic package layer is used for sealing the chip, the columnar salient points and the lead frames and exposing the external pins.

Abstract: The present invention provides a semiconductor package structure, including: a chip, wherein bonding pads and a passivation layer are arranged on the surface of the chip, the passivation layer is provided with first openings for exposing the bonding pads, and a seed layer connected with the bonding pads and columnar salient points stacked on the seed layer are arranged on the bonding pads; lead frames, wherein each lead frame is provided with a plurality of discrete pins, and internal pins and external pins are respectively arranged on two opposite surfaces of the pins; the chip being flipped on the lead frames, and the columnar salient points being connected with the internal pins; a plastic package layer, wherein the plastic package layer is used for sealing the chip, the columnar salient points and the lead frames and exposing the external pins.

Abstract: The present invention provides a wafer packaging structure and a wafer packaging method. The wafer packaging structure includes: a substrate, wherein grooves are formed in one surface of the substrate, and chips are arranged in the grooves; a material sealing layer formed on the substrate, wherein connecting components of the chips are exposed from the surface of the material sealing layer; a wiring layer formed on the material sealing layer and electrically connected with the connecting components; a protective film layer formed on the wiring layer, wherein the protective film layer is provided with openings for exposing the wiring layer; lower ball metal layers formed in the openings and connected with the wiring layer; and metal balls formed on the lower ball metal layers. The wafer packaging structure provided by the present invention can be used for packaging a plurality of chips, thereby having a higher integration level and a higher integration degree.

Abstract: A semiconductor device may include a first line of vias including a first via and a second via immediately adjacent to the first via. The semiconductor device may further include a second line of vias arranged immediately adjacent to and parallel to the first line of vias, the second line of vias including a third via immediately adjacent to the first via and the second via, the second line of vias further including a fourth via immediately adjacent to the third via, the first via, and the second via. The shortest distance between the second via and the fourth via may be greater than the shortest distance between the first via and the second via.