Abstract: A non-volatile memory device includes a memory cell array including memory cells respectively connected to bit lines; and a control logic unit configured to control a program operation with respect to the memory cells. The control logic unit is configured to perform a normal program verify operation with respect to the memory cells by using a normal program verify condition, during the program operation, and, based on a suspend command that is received during the program operation, perform an initial program verify operation with respect to the memory cells by using an initial program verify condition that is different from the normal program verify condition.

Abstract: An operating method of a nonvolatile memory device for programming multi-page data, the operating method including: receiving the multi-page data from a memory controller; programming first page data among the multi-page data to first memory cells connected to a word line adjacent to a selected word line; reading previous page data previously stored in second memory cells connected to the selected word line based on a first sensing value and a second sensing value after programming the first page data; calculating a first fail bit number by comparing first bits of the previous page data read based on the first sensing value to second bits of the previous page data read based on the second sensing value; and programming the previous page data read from the second memory cells and second page data among the multi-page data to the second memory cells based on the first fail bit number.

Abstract: An operating method of a nonvolatile memory device for programming multi-page data, the operating method including: receiving the multi-page data from a memory controller; programming first page data among the multi-page data to first memory cells connected to a word line adjacent to a selected word line; reading previous page data previously stored in second memory cells connected to the selected word line based on a first sensing value and a second sensing value after programming the first page data; calculating a first fail bit number by comparing first bits of the previous page data read based on the first sensing value to second bits of the previous page data read based on the second sensing value; and programming the previous page data read from the second memory cells and second page data among the multi-page data to the second memory cells based on the first fail bit number.

Abstract: An operating method of a non-volatile memory device, the method including: receiving a program command from an external device; determining an operating mode in response to the program command; when the operating mode is a surface mount technology (SMT) mode, performing an initial program operation in which a plurality of memory cells are programmed through a plurality of steps to form a first threshold voltage distribution; and when the operating mode is a normal mode, performing a normal program operation in which the plurality of memory cells are programmed through a single step to form a second threshold voltage distribution, wherein the first threshold voltage distribution is narrower in width than the second threshold voltage distribution.

Abstract: An operating method of a nonvolatile memory device for programming multi-page data, the operating method including: receiving the multi-page data from a memory controller; programming first page data among the multi-page data to first memory cells connected to a word line adjacent to a selected word line; reading previous page data previously stored in second memory cells connected to the selected word line based on a first sensing value and a second sensing value after programming the first page data; calculating a first fail bit number by comparing first bits of the previous page data read based on the first sensing value to second bits of the previous page data read based on the second sensing value; and programming the previous page data read from the second memory cells and second page data among the multi-page data to the second memory cells based on the first fail bit number.

Abstract: A memory device includes a cell region in which memory blocks are disposed, each memory block including word lines stacked on a substrate, and channel structures penetrating through the word lines, and a peripheral circuit region including peripheral circuits executing an erase operation of deleting data for each of the memory blocks as a unit. The peripheral circuits control a voltage applied to each word line included in a target memory block to delete data in the erase operation, based on at least one of a position of the target memory block, a height of each word line included in the target memory block, and a profile of each channel structure.

Abstract: An operating method of a nonvolatile memory device for programming multi-page data, the operating method including: receiving the multi-page data from a memory controller; programming first page data among the multi-page data to first memory cells connected to a word line adjacent to a selected word line; reading previous page data previously stored in second memory cells connected to the selected word line based on a first sensing value and a second sensing value after programming the first page data, calculating a first fail bit number by comparing first bits of the previous page data read based on the first sensing value to second bits of the previous page data read based on the second sensing value; and programming the previous page data read from the second memory cells and second page data among the multi-page data to the second memory cells based on the first fail bit number.

Abstract: A program method of a non-volatile memory device, the non-volatile memory device including a cell string having memory cells stacked perpendicular to a surface of a substrate, the method includes performing a first program phase including programming a first memory cell connected to a first word line and applying a first pass voltage to other word lines above or below the first word line, and performing a second program phase including programming a second memory cell after the first memory cell is completely programmed, the second memory cell being connected to a second word line closer to the substrate than the first word line, applying a second pass voltage to a first word line group below the second word line and applying a third pass voltage to a second word line group above the second word line, the second pass voltage being lower than the third pass voltage.

Abstract: A program method of a non-volatile memory device, the non-volatile memory device including a peripheral circuit region and a memory cell region including a cell substrate and a cell string having memory cells stacked perpendicular to a surface of a cell substrate, the method includes performing a first program phase including programming a first memory cell connected to a first word line and applying a first pass voltage to other word lines above or below the first word line, and performing a second program phase including programming a second memory cell being connected to a second word line closer to the cell substrate, applying a second pass voltage to a first word line group below the second word line and applying a third pass voltage to a second word line group above the second word line, the second pass voltage being lower than the third pass voltage.

Abstract: A memory device includes a cell region in which memory blocks are disposed, each memory block including word lines stacked on a substrate, and channel structures penetrating through the word lines, and a peripheral circuit region including peripheral circuits executing an erase operation of deleting data for each of the memory blocks as a unit. The peripheral circuits control a voltage applied to each word line included in a target memory block to delete data in the erase operation, based on at least one of a position of the target memory block, a height of each word line included in the target memory block, and a profile of each channel structure.

Abstract: An operating method of a nonvolatile memory device for programming multi-page data, the operating method including: receiving the multi-page data from a memory controller; programming first page data among the multi-page data to first memory cells connected to a word line adjacent to a selected word line; reading previous page data previously stored in second memory cells connected to the selected word line based on a first sensing value and a second sensing value after programming the first page data, calculating a first fail bit number by comparing first bits of the previous page data read based on the first sensing value to second bits of the previous page data read based on the second sensing value; and programming the previous page data read from the second memory cells and second page data among the multi-page data to the second memory cells based on the first fail bit number.

Abstract: A non-volatile memory device includes a memory cell array including memory cells respectively connected to bit lines; and a control logic unit configured to control a program operation with respect to the memory cells. The control logic unit is configured to perform a normal program verify operation with respect to the memory cells by using a normal program verify condition, during the program operation, and, based on a suspend command that is received during the program operation, perform an initial program verify operation with respect to the memory cells by using an initial program verify condition that is different from the normal program verify condition.

Abstract: A non-volatile memory device includes a memory cell array including memory cells respectively connected to bit lines; and a control logic unit configured to control a program operation with respect to the memory cells. The control logic unit is configured to perform a normal program verify operation with respect to the memory cells by using a normal program verify condition, during the program operation, and, based on a suspend command that is received during the program operation, perform an initial program verify operation with respect to the memory cells by using an initial program verify condition that is different from the normal program verify condition.

Abstract: A non-volatile memory device includes a memory cell array including memory cells respectively connected to bit lines; and a control logic unit configured to control a program operation with respect to the memory cells. The control logic unit is configured to perform a normal program verify operation with respect to the memory cells by using a normal program verify condition, during the program operation, and, based on a suspend command that is received during the program operation, perform an initial program verify operation with respect to the memory cells by using an initial program verify condition that is different from the normal program verify condition.

Abstract: A program method of a non-volatile memory device, the non-volatile memory device including a cell string having memory cells stacked perpendicular to a surface of a substrate, the method includes performing a first program phase including programming a first memory cell connected to a first word line and applying a first pass voltage to other word lines above or below the first word line, and performing a second program phase including programming a second memory cell after the first memory cell is completely programmed, the second memory cell being connected to a second word line closer to the substrate than the first word line, applying a second pass voltage to a first word line group below the second word line and applying a third pass voltage to a second word line group above the second word line, the second pass voltage being lower than the third pass voltage.

Abstract: A program method of a non-volatile memory device, the non-volatile memory device including a peripheral circuit region and a memory cell region including a cell substrate and a cell string having memory cells stacked perpendicular to a surface of a cell substrate, the method includes performing a first program phase including programming a first memory cell connected to a first word line and applying a first pass voltage to other word lines above or below the first word line, and performing a second program phase including programming a second memory cell being connected to a second word line closer to the cell substrate, applying a second pass voltage to a first word line group below the second word line and applying a third pass voltage to a second word line group above the second word line, the second pass voltage being lower than the third pass voltage.

Abstract: A non-volatile memory device includes a memory cell array including memory cells respectively connected to bit lines; and a control logic unit configured to control a program operation with respect to the memory cells. The control logic unit is configured to perform a normal program verify operation with respect to the memory cells by using a normal program verify condition, during the program operation, and, based on a suspend command that is received during the program operation, perform an initial program verify operation with respect to the memory cells by using an initial program verify condition that is different from the normal program verify condition.

Abstract: A non-volatile memory device includes a memory cell array including memory cells respectively connected to bit lines; and a control logic unit configured to control a program operation with respect to the memory cells. The control logic unit is configured to perform a normal program verify operation with respect to the memory cells by using a normal program verify condition, during the program operation, and, based on a suspend command that is received during the program operation, perform an initial program verify operation with respect to the memory cells by using an initial program verify condition that is different from the normal program verify condition.

Abstract: A nonvolatile memory device performs a method which includes: causing a ready/busy signal pin of the nonvolatile memory device to indicate that the nonvolatile memory device is in a precharge busy state wherein the nonvolatile memory device is not available to perform memory access operations for its nonvolatile memory cells; applying one or more word line precharge voltages to one or more selected word lines among a plurality of word lines of the nonvolatile memory device to precharge the selected word lines; and, after at least a portion of the precharge operation, causing the ready/busy signal pin to transition from indicating the precharge busy state, to indicating that the nonvolatile memory device is in a ready state wherein the nonvolatile memory device is available to perform memory access operations for its nonvolatile memory cells.

Abstract: A nonvolatile memory device performs a method which includes: causing a ready/busy signal pin of the nonvolatile memory device to indicate that the nonvolatile memory device is in a precharge busy state wherein the nonvolatile memory device is not available to perform memory access operations for its nonvolatile memory cells; applying one or more word line precharge voltages to one or more selected word lines among a plurality of word lines of the nonvolatile memory device to precharge the selected word lines; and, after at least a portion of the precharge operation, causing the ready/busy signal pin to transition from indicating the precharge busy state, to indicating that the nonvolatile memory device is in a ready state wherein the nonvolatile memory device is available to perform memory access operations for its nonvolatile memory cells.