Patents by Inventor Wanfang Tsai
Wanfang Tsai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10297337Abstract: Apparatuses and techniques for counting 0 or 1 bits in a set of bits using both serial and parallel processes. The counting process includes a hierarchy in which the count from different parallel processes at one level in the hierarchy are passed to a smaller number of different parallel processes at a lower level in the hierarchy. A final count is obtained by an accumulator below the lowest level of the hierarchy. The position and configuration of the circuits can be set to equalize a number of circuits which process the different bits, so that a maximum delay relative to the accumulator is equalized.Type: GrantFiled: August 4, 2017Date of Patent: May 21, 2019Assignee: SanDisk Technologies LLCInventors: Wanfang Tsai, Hung-Szu Lin, Yi-Fang Chen
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Publication number: 20190043603Abstract: Apparatuses and techniques for counting 0 or 1 bits in a set of bits using both serial and parallel processes. The counting process includes a hierarchy in which the count from different parallel processes at one level in the hierarchy are passed to a smaller number of different parallel processes at a lower level in the hierarchy. A final count is obtained by an accumulator below the lowest level of the hierarchy. The position and configuration of the circuits can be set to equalize a number of circuits which process the different bits, so that a maximum delay relative to the accumulator is equalized.Type: ApplicationFiled: August 4, 2017Publication date: February 7, 2019Applicant: SanDisk Technologies LLCInventors: Wanfang Tsai, Hung-Szu Lin, Yi-Fang Chen
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Patent number: 10120816Abstract: Systems and methods for controlling data flow and data alignment using data expand and compress circuitry arranged between a variable data rate bi-directional first in, first out (FIFO) buffer and one or more memory arrays to compensate for bad column locations within the one or more memory arrays are described. The bi-directional FIFO may have a variable data rate with the array side and a fixed data rate with a serializer/deserializer (SERDES) circuit that drives input/output (I/O) circuitry. The data expand and compress circuitry may pack and unpack data and then align the data passing between the one or more memory arrays and the bi-directional FIFO using a temporary buffer, data shuffling logic, and selective pipeline stalls.Type: GrantFiled: March 14, 2017Date of Patent: November 6, 2018Assignee: SANDISK TECHNOLOGIES LLCInventors: Wanfang Tsai, Yan Li
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Publication number: 20180024948Abstract: Systems and methods for controlling data flow and data alignment using data expand and compress circuitry arranged between a variable data rate bi-directional first in, first out (FIFO) buffer and one or more memory arrays to compensate for bad column locations within the one or more memory arrays are described. The bi-directional FIFO may have a variable data rate with the array side and a fixed data rate with a serializer/deserializer (SERDES) circuit that drives input/output (I/O) circuitry. The data expand and compress circuitry may pack and unpack data and then align the data passing between the one or more memory arrays and the bi-directional FIFO using a temporary buffer, data shuffling logic, and selective pipeline stalls.Type: ApplicationFiled: March 14, 2017Publication date: January 25, 2018Applicant: SANDISK TECHNOLOGIES LLCInventors: Wanfang Tsai, Yan Li
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Patent number: 9875156Abstract: A data storage device includes a set of latches, read/write circuitry, a memory, and an interleaver. The set of latches is configured to receive data. The read/write circuitry is coupled to the set of latches. The memory is coupled to the read/write circuitry. The interleaver is configured to interleave the data and to cause the read/write circuitry to program the interleaved data to the memory. The set of latches, the read/write circuitry, the memory, and the interleaver are integrated within a common die.Type: GrantFiled: October 1, 2015Date of Patent: January 23, 2018Assignee: SanDisk Technologies LLCInventors: Eran Sharon, Ariel Navon, Alexander Tsang-Nam Chu, Wanfang Tsai, Idan Alrod
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Patent number: 9703719Abstract: Sensing techniques and associated circuitry are provided for use with a memory device. The techniques are suited for sensing operations involving even-numbered or odd-numbered bit lines. In one approach, the sensing circuitry includes left and right hand portions which have separate cache access lines, but are connected to a common output bus. A full data word can be output at a time by using a half word from the left hand portion and a half word from the right hand portion. Or, the sensing circuitry can be configured so that a full data word is output at a time from the left or right hand portion. One implementation provides an N-bit bus and N input paths for each of the left and right hand portions. Another implementation provides an N-bit bus and N/2 input paths for each of the left and right hand portions.Type: GrantFiled: October 30, 2015Date of Patent: July 11, 2017Assignee: SanDisk Technologies LLCInventors: Gopinath Balakrishnan, Chang Siau, Yosuke Kato, Wanfang Tsai, Shingo Zaitsu
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Publication number: 20170097869Abstract: A data storage device includes a set of latches, read/write circuitry, a memory, and an interleaver. The set of latches is configured to receive data. The read/write circuitry is coupled to the set of latches. The memory is coupled to the read/write circuitry. The interleaver is configured to interleave the data and to cause the read/write circuitry to program the interleaved data to the memory. The set of latches, the read/write circuitry, the memory, and the interleaver are integrated within a common die.Type: ApplicationFiled: October 1, 2015Publication date: April 6, 2017Inventors: ERAN SHARON, ARIEL NAVON, ALEXANDER TSANG-NAM CHU, WANFANG TSAI, IDAN ALROD
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Patent number: 9583220Abstract: A memory circuit includes an array subdivided into multiple divisions, each connectable to a corresponding set of access circuitry. A serializer/deserializer circuit is connected to a data bus and the access circuitry to convert data between a (word-wise) serial format on the bus and (multi-word) parallel format for the access circuitry. Column redundancy circuitry is connect to the serializer/deserializer circuit to provide defective column information about the array. In converting data from a serial to a parallel format, the serializer/deserializer circuit skips words of the data in the parallel format based on the defective column information indicating that the location corresponds to a defective column. In converting data from a parallel to a serial format the serializer/deserializer circuit skips words of the data in the parallel format based on the defective column information indicating that the location corresponds to a defective column.Type: GrantFiled: June 28, 2016Date of Patent: February 28, 2017Assignee: SANDISK TECHNOLOGIES LLCInventors: Wanfang Tsai, YenLung Li, Chen Chen
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Publication number: 20160328321Abstract: Sensing techniques and associated circuitry are provided for use with a memory device. The techniques are suited for sensing operations involving even-numbered or odd-numbered bit lines. In one approach, the sensing circuitry includes left and right hand portions which have separate cache access lines, but are connected to a common output bus. A full data word can be output at a time by using a half word from the left hand portion and a half word from the right hand portion. Or, the sensing circuitry can be configured so that a full data word is output at a time from the left or right hand portion. One implementation provides an N-bit bus and N input paths for each of the left and right hand portions. Another implementation provides an N-bit bus and N/2 input paths for each of the left and right hand portions.Type: ApplicationFiled: October 30, 2015Publication date: November 10, 2016Applicant: SANDISK TECHNOLOGIES INC.Inventors: Gopinath Balakrishnan, Chang Siau, Yosuke Kato, Wanfang Tsai, Shingo Zaitsu
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Patent number: 9490035Abstract: A memory circuit includes an array subdivided into multiple divisions, each connectable to a corresponding set of access circuitry. A serializer/deserializer circuit is connected to a data bus and the access circuitry to convert data between a (word-wise) serial format on the bus and (multi-word) parallel format for the access circuitry. Column redundancy circuitry is connect to the serializer/deserializer circuit to provide defective column information about the array. In converting data from a serial to a parallel format, the serializer/deserializer circuit skips words of the data in the parallel format based on the defective column information indicating that the location corresponds to a defective column. In converting data from a parallel to a serial format the serializer/deserializer circuit skips words of the data in the parallel format based on the defective column information indicating that the location corresponds to a defective column.Type: GrantFiled: December 12, 2013Date of Patent: November 8, 2016Assignee: SanDisk Technologies, Inc.Inventors: Wanfang Tsai, YenLung Li, Chen Chen
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Publication number: 20160307634Abstract: A memory circuit includes an array subdivided into multiple divisions, each connectable to a corresponding set of access circuitry. A serializer/deserializer circuit is connected to a data bus and the access circuitry to convert data between a (word-wise) serial format on the bus and (multi-word) parallel format for the access circuitry. Column redundancy circuitry is connect to the serializer/deserializer circuit to provide defective column information about the array. In converting data from a serial to a parallel format, the serializer/deserializer circuit skips words of the data in the parallel format based on the defective column information indicating that the location corresponds to a defective column. In converting data from a parallel to a serial format the serializer/deserializer circuit skips words of the data in the parallel format based on the defective column information indicating that the location corresponds to a defective column.Type: ApplicationFiled: June 28, 2016Publication date: October 20, 2016Applicant: SanDisk Technologies, Inc.Inventors: Wanfang TSAI, YenLung LI, Chen CHEN
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Patent number: 9329986Abstract: Techniques are presented to operate a greater number of dice in parallel while not exceeding peak current limits. The device can arbitrate between multiple dice and, when needed, suspend operations on one or more dice in a way to average the chance of performance penalty so that all chips will proceed with write at an equal probability. In other aspects, the suspension of operations can be weighted based on factors such as the relative speed of the different dice or differing loads.Type: GrantFiled: March 5, 2013Date of Patent: May 3, 2016Assignee: SanDisk Technologies Inc.Inventors: Yan Li, Yacov Duzly, Frank Wanfang Tsai, Alon Marcu
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Patent number: 9076506Abstract: A shift register structure is presented that can be used in variable rate parallel to serial data conversions. In an N to 1 conversion, data is received from an (N×m)-wide parallel data bus in an N by m wide latch. This data can include m-bit wide units of data are to be ignore and the parallel bus clock will be of variable rate due to this data to be skipped, which is not to be put out on to the serial bus. The data is transferred from the latch to an N unit shift register, each unit holding m-bits. Multiplexing circuitry is included so that at least on unit of the shift can receive data from more than one latch location, thereby reducing the number of units in the shift register that may need to be skipped when the data is transferred out on to an m-bit wide serial bus with the bits to be ignored absent.Type: GrantFiled: September 28, 2012Date of Patent: July 7, 2015Assignee: SanDisk Technologies Inc.Inventor: Wanfang Tsai
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Patent number: 8897080Abstract: A shift register structure is presented that can be used in fixed or variable rate serial to parallel data conversions. In an 1 to N conversion, data is received off an m-bit serial data bus and loaded into a N by m wide latch, before being transfer out onto an (N×m)-wide parallel data bus. Based on information on how of the N m-bit wide data units are to be ignored, the data will be clocked out at a variable rate. When loading data off the serial bus into the latch, upon refresh the current data is loaded into all N units of the latch, with one less latch being loaded at each subsequent clock. When the content of a unit of latch is to be ignored on the parallel bus, that unit is closed at the same time as the preceding unit so that it is left with redundant data.Type: GrantFiled: September 28, 2012Date of Patent: November 25, 2014Assignee: SanDisk Technologies Inc.Inventor: Wanfang Tsai
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Patent number: 8842473Abstract: Techniques are present for locating an initial physical location in a looping shift register with random skips on each loop. Here the shift register is for accessing columns in a non-volatile memory, where defective columns of the array are skipped. A look-up table provides for the initial skip of each loop, providing the number of skips from preceding loop to provide a physical address is close to the actual physical address. A new structure of shift registers then enables an automatic shift mode within the loop. The new structure has an additional register and logic gates that count how many skipped entry before the current pointer and shift the current pointer accordingly.Type: GrantFiled: March 15, 2012Date of Patent: September 23, 2014Assignee: SanDisk Technologies Inc.Inventor: Wanfang Tsai
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Publication number: 20140126293Abstract: A memory circuit includes an array subdivided into multiple divisions, each connectable to a corresponding set of access circuitry. A serializer/deserializer circuit is connected to a data bus and the access circuitry to convert data between a (word-wise) serial format on the bus and (multi-word) parallel format for the access circuitry. Column redundancy circuitry is connect to the serializer/deserializer circuit to provide defective column information about the array. In converting data from a serial to a parallel format, the serializer/deserializer circuit skips words of the data in the parallel format based on the defective column information indicating that the location corresponds to a defective column. In converting data from a parallel to a serial format the serializer/deserializer circuit skips words of the data in the parallel format based on the defective column information indicating that the location corresponds to a defective column.Type: ApplicationFiled: December 12, 2013Publication date: May 8, 2014Applicant: SanDisk Technologies IncInventors: Wanfang Tsai, YenLung Li, Chen Chen
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Publication number: 20140092692Abstract: A shift register structure is presented that can be used in fixed or variable rate serial to parallel data conversions. In an 1 to N conversion, data is received off an m-bit serial data bus and loaded into a N by m wide latch, before being transfer out onto an (N×m)-wide parallel data bus. Based on information on how of the N m-bit wide data units are to be ignored, the data will be clocked out at a variable rate. When loading data off the serial bus into the latch, upon refresh the current data is loaded into all N units of the latch, with one less latch being loaded at each subsequent clock. When the content of a unit of latch is to be ignored on the parallel bus, that unit is closed at the same time as the preceding unit so that it is left with redundant data.Type: ApplicationFiled: September 28, 2012Publication date: April 3, 2014Inventor: Wanfang Tsai
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Publication number: 20140092690Abstract: A shift register structure is presented that can be used in variable rate parallel to serial data conversions. In an N to I conversion, data is received from an (N×m)-wide parallel data bus in an N by in wide latch. This data can include m-bit wide units of data are to be ignore and the parallel bus clock will be of variable rate due to this data to be skipped, which is not to be put out on to the serial bus. The data is transferred from the latch to an N unit shift register, each unit holding m-bits. Multiplexing circuitry is included so that at least on unit of the shift can receive data from more than one latch location, thereby reducing the number of units in the shift register that may need to be skipped when the data is transferred out on to an m-bit wide serial bus with the bits to be ignored absent.Type: ApplicationFiled: September 28, 2012Publication date: April 3, 2014Inventor: Wanfang Tsai
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Patent number: 8681548Abstract: In a non-volatile memory circuit, techniques are presented so that bad columns can be ignored and/or replaced during memory data input and output operations. A column redundant circuit for this purpose reduces circuit size and improves performance. User data is grouped in an interleaved manner so that data belonging to consecutive logical address will be distributed into different physical locations. For example, all column data can be physically grouped into, say, 5 divisions and user data can be written into or accessed from one division after another consecutively. Each division has its own clock control. The column redundancy block can generate bad column locations' information and send it to control logic to switch the user clock to a different division clock, thereby skipping bad columns. By controlling the clocks for different columns, the user can directly access good columns without touching bad columns.Type: GrantFiled: May 3, 2012Date of Patent: March 25, 2014Assignee: SanDisk Technologies Inc.Inventors: Bo Liu, Frank Wanfang Tsai, Jongmin Park, Yan Li
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Publication number: 20140075133Abstract: Techniques are presented to operate a greater number of dice in parallel while not exceeding peak current limits. The device can arbitrate between multiple dice and, when needed, suspend operations on one or more dice in a way to average the chance of performance penalty so that all chips will proceed with write at an equal probability. In other aspects, the suspension of operations can be weighted based on factors such as the relative speed of the different dice or differing loads.Type: ApplicationFiled: March 5, 2013Publication date: March 13, 2014Applicant: SANDISK TECHNOLOGIES INC.Inventors: Yan Li, Yacov Duzly, Frank Wanfang Tsai, Alon Marcu