Patents by Inventor Wang-Chun Huang

Wang-Chun Huang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10971609
    Abstract: An integrated circuit (IC) structure with a nanowire power switch device and a method of forming the IC structure are disclosed. The method includes forming a first layer of metal lines of a first back end of line (BEOL) interconnect structure and forming a semiconductor nanowire structure on a first metal line of the first layer of metal lines. The BEOL interconnect structure is formed on a front end of line (FEOL) device layer having multiple active devices. The method further includes forming a first dielectric layer wrapped around the semiconductor nanowire structure, forming a metal layer on the dielectric layer and on a second metal line of the first layer of metal lines, and forming a second layer of metal lines of a second BEOL interconnect structure on the semiconductor nanowire structure. The first and second metal lines are electrically isolated from each other.
    Type: Grant
    Filed: August 23, 2019
    Date of Patent: April 6, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Li-Yang Chuang, Ching-Wei Tsai, Wang-Chun Huang, Kuan-Lun Cheng
  • Publication number: 20210098450
    Abstract: The present disclosure describes a method to form a fin field effect transistor (finFET) and a nano-sheet transistor on a substrate. The method can include forming first and second vertical structures over a substrate, where each of the first and the second vertical structures can include a buffer region and a first channel layer formed over the buffer region. The method can further include disposing a masking layer over the first channel layer of the first and second vertical structures, removing a portion of the first vertical structure to form a first recess, forming a second channel layer in the first recess, forming a second recess in the second channel layer, and disposing an insulating layer in the second recess.
    Type: Application
    Filed: October 1, 2019
    Publication date: April 1, 2021
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Wang-Chun Huang, Chih-Hao Wang, Ching-Wei Tsai, Kuan-Lun Cheng
  • Publication number: 20210057559
    Abstract: An integrated circuit (IC) structure with a nanowire power switch device and a method of forming the IC structure are disclosed. The method includes forming a first layer of metal lines of a first back end of line (BEOL) interconnect structure and forming a semiconductor nanowire structure on a first metal line of the first layer of metal lines. The BEOL interconnect structure is formed on a front end of line (FEOL) device layer having multiple active devices. The method further includes forming a first dielectric layer wrapped around the semiconductor nanowire structure, forming a metal layer on the dielectric layer and on a second metal line of the first layer of metal lines, and forming a second layer of metal lines of a second BEOL interconnect structure on the semiconductor nanowire structure. The first and second metal lines are electrically isolated from each other.
    Type: Application
    Filed: August 23, 2019
    Publication date: February 25, 2021
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Li-Yang Chuang, Ching-Wei Tsai, Wang-Chun Huang, Kuan-Lun Cheng
  • Publication number: 20210057541
    Abstract: A structure and formation method of a semiconductor device is provided. The method includes forming a semiconductor stack having first sacrificial layers and first semiconductor layers laid out alternately. The method also includes patterning the semiconductor stack to form a first fin structure and a second fin structure. The method further includes replacing the second fin structure with a third fin structure having second sacrificial layers and second semiconductor layers laid out alternately. In addition, the method includes removing the first sacrificial layers in the first fin structure and the second sacrificial layers in the third fin structure. The method includes forming a first metal gate stack and a second metal gate stack to wrap around each of the first semiconductor layers in the first fin structure and each of the second semiconductor layers in the third fin structure, respectively.
    Type: Application
    Filed: August 22, 2019
    Publication date: February 25, 2021
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Wang-Chun Huang, Ching-Wei Tsai, Kuan-Lun Cheng, Chih-Hao Wang
  • Publication number: 20200343273
    Abstract: A finFET device that includes a substrate and at least one semiconductor fin extending from the substrate. The fin may include a plurality of wide portions comprising a first semiconductor material and one or more narrow portions. The one or more narrow portions have a second width less than the first width of the wide portions. Each of the one or more narrow portions separates two of the plurality of wide portions from one another such that the plurality of wide portions and the one or more narrow portions are arranged alternatingly in a substantially vertical direction that is substantially perpendicular with a surface of the substrate. The fin may also include a channel layer covering sidewalls of the plurality of wide portions and a sidewall of the one or more narrow portions.
    Type: Application
    Filed: April 26, 2019
    Publication date: October 29, 2020
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wang-Chun Huang, Kai-Chieh Yang, Ching-Wei Tsai, Kuan-Lun Chen, Chih-Hao Wang
  • Patent number: 10326023
    Abstract: A method for manufacturing a semiconductor device includes forming a fin structure having a top face and a first side face and a second side face opposite to the first side face, forming a lower cover layer over the first and second side faces, forming an upper cover layer over the first and second side faces, the upper cover layer being spaced apart from the lower cover layer so that exposed regions of the first and second side faces are formed between the lower cover layer and the upper cover layer, and forming first and second semiconductor layers over the exposed regions of the first and second side faces, respectively.
    Type: Grant
    Filed: May 7, 2018
    Date of Patent: June 18, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Tung Ying Lee, Chien-Chang Su, Wang-Chun Huang, Yasutoshi Okuno
  • Publication number: 20180254347
    Abstract: A method for manufacturing a semiconductor device includes forming a fin structure having a top face and a first side face and a second side face opposite to the first side face, forming a lower cover layer over the first and second side faces, forming an upper cover layer over the first and second side faces, the upper cover layer being spaced apart from the lower cover layer so that exposed regions of the first and second side faces are formed between the lower cover layer and the upper cover layer, and forming first and second semiconductor layers over the exposed regions of the first and second side faces, respectively.
    Type: Application
    Filed: May 7, 2018
    Publication date: September 6, 2018
    Inventors: Tung Ying LEE, Chien-Chang SU, Wang-Chun HUANG, Yasutoshi OKUNO
  • Patent number: 9966469
    Abstract: A method for manufacturing a semiconductor device includes forming a fin structure having a top face and a first side face and a second side face opposite to the first side face, forming a lower cover layer over the first and second side faces, forming an upper cover layer over the first and second side faces, the upper cover layer being spaced apart from the lower cover layer so that exposed regions of the first and second side faces are formed between the lower cover layer and the upper cover layer, and forming first and second semiconductor layers over the exposed regions of the first and second side faces, respectively.
    Type: Grant
    Filed: February 22, 2017
    Date of Patent: May 8, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Tung Ying Lee, Chien-Chang Su, Wang-Chun Huang, Yasutoshi Okuno
  • Publication number: 20170162696
    Abstract: A method for manufacturing a semiconductor device includes forming a fin structure having a top face and a first side face and a second side face opposite to the first side face, forming a lower cover layer over the first and second side faces, forming an upper cover layer over the first and second side faces, the upper cover layer being spaced apart from the lower cover layer so that exposed regions of the first and second side faces are formed between the lower cover layer and the upper cover layer, and forming first and second semiconductor layers over the exposed regions of the first and second side faces, respectively.
    Type: Application
    Filed: February 22, 2017
    Publication date: June 8, 2017
    Inventors: Tung Ying LEE, Chien-Chang SU, Wang-Chun HUANG, Yasutoshi OKUNO
  • Patent number: 9601626
    Abstract: A semiconductor device includes a fin structure protruding from a substrate and having a top face and a first side face and a second side face opposite to the first side face, and first semiconductor layers disposed over the first and second side faces of the fin structure. A thickness in a vertical direction of the first semiconductor layers is smaller than a height of the fin structure.
    Type: Grant
    Filed: January 23, 2015
    Date of Patent: March 21, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Tung Ying Lee, Yasutoshi Okuno, Chien-Chang Su, Wang-Chun Huang
  • Publication number: 20160218217
    Abstract: A semiconductor device includes a fin structure protruding from a substrate and having a top face and a first side face and a second side face opposite to the first side face, and first semiconductor layers disposed over the first and second side faces of the fin structure. A thickness in a vertical direction of the first semiconductor layers is smaller than a height of the fin structure.
    Type: Application
    Filed: January 23, 2015
    Publication date: July 28, 2016
    Inventors: Tung Ying Lee, Yasutoshi Okuno, Chien-Chang Su, Wang-Chun Huang