Patents by Inventor Wang Hai YING

Wang Hai YING has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Semiconductor structure and method for forming same
    Patent number: 11069694
    Abstract: A semiconductor structure and a method for forming same are provided. In one form a method includes: providing a substrate with a discrete first gate laminated structure formed on the substrate; forming, on a portion of the substrate exposed from the first gate laminated structure, a unit dielectric layer covering a portion of a side wall of the first gate laminated structure, where the first gate laminated structure and the unit dielectric layer enclose a unit groove; forming an isolation spacer layer on a side wall of the unit groove, where the isolation spacer layer is in contact with the unit dielectric layer; forming a metal layer conformally covering the isolation spacer layer, the first gate laminated structure, and the unit dielectric layer; and annealing the metal layer to form a metal silicide layer.
    Type: Grant
    Filed: March 13, 2020
    Date of Patent: July 20, 2021
    Assignees: Semiconductor Manufacturing (Shanghai) International Corporation, Semiconductor Manufacturing (Beijing) International Corporation
    Inventors: Han Liang, Wang Hai Ying
  • SEMICONDUCTOR STRUCTURE AND METHOD FOR FORMING SAME
    Publication number: 20210066326
    Abstract: A semiconductor structure and a method for forming same are provided. In one form a method includes: providing a substrate with a discrete first gate laminated structure formed on the substrate; forming, on a portion of the substrate exposed from the first gate laminated structure, a unit dielectric layer covering a portion of a side wall of the first gate laminated structure, where the first gate laminated structure and the unit dielectric layer enclose a unit groove; forming an isolation spacer layer on a side wall of the unit groove, where the isolation spacer layer is in contact with the unit dielectric layer; forming a metal layer conformally covering the isolation spacer layer, the first gate laminated structure, and the unit dielectric layer; and annealing the metal layer to form a metal silicide layer.
    Type: Application
    Filed: March 13, 2020
    Publication date: March 4, 2021
    Applicants: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) Corporation
    Inventors: Han LIANG, Wang Hai YING