Patents by Inventor Wanghua CHEN

Wanghua CHEN has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11574807
    Abstract: The invention relates to a process for the preparation of a semiconductor material comprising at least one entirely monocrystalline semiconductor layer, said process comprising the steps of preparation of the surface of a first substrate to receive a monocrystalline silicon layer; deposition by Plasma-Enhanced Chemical Vapor Deposition (PECVD) of a layer of monocrystalline silicon by epitaxial growth with a growth rate gradient on the silicon layer monocrystalline obtained in step (i); and epitaxial growth of a monocrystalline layer of a semiconductor material on the monocrystalline silicon layer obtained in step (ii), to thus obtain a material comprising at least one entirely monocrystalline semiconductor layer. The invention also relates to a multilayer material comprising a monocrystalline layer of semiconductor material.
    Type: Grant
    Filed: November 15, 2018
    Date of Patent: February 7, 2023
    Assignees: CENTRE NATIONAL DE LA RECHERCHE SCIENTIFIQUE, INSTITUT PHOTOVOLTAÏQUE D'ILE DE FRANCE (IPVF), ECOLE POLYTECHNIQUE, TOTALENERGIES SE, ELECTRICITE DE FRANCE
    Inventors: Père Roca I Cabaroccas, Wanghua Chen, Romain Cariou
  • Publication number: 20200395212
    Abstract: The invention relates to a process for the preparation of a semiconductor material comprising at least one entirely monocrystalline semiconductor layer, said process comprising the steps of preparation of the surface of a first substrate to receive a monocrystalline silicon layer; deposition by Plasma-Enhanced Chemical Vapor Deposition (PECVD) of a layer of monocrystalline silicon by epitaxial growth with a growth rate gradient on the silicon layer monocrystalline obtained in step (i); and epitaxial growth of a monocrystalline layer of a semiconductor material on the monocrystalline silicon layer obtained in step (ii), to thus obtain a material comprising at least one entirely monocrystalline semiconductor layer. The invention also relates to a multilayer material comprising a monocrystalline layer of semiconductor material.
    Type: Application
    Filed: November 15, 2018
    Publication date: December 17, 2020
    Applicants: Centre national de la recherche scientifique, INSTITUT PHOTOVOLTAÏQUE D'lLE DE FRANCE (IPVF), ECOLE POLYTECHNIQUE, L'AIR LIQUIDE, SOCIETE ANONYME POUR L'ETUDE ET L'EXPLOITATION DES PROCEDES GEORGES CLAUDE, TOTAL SA, ELECTRICITE DE FRANCE
    Inventors: Père ROCA I CABAROCCAS, Wanghua CHEN, Romain CARIOU
  • Patent number: 10763381
    Abstract: Disclosed is an opto-electronic device including a semiconducting substrate, a layered interface including at least one layer, the layered interface having a first surface in contact with a surface of the semiconducting substrate and the layered interface being adapted for passivating the surface of the semiconducting substrate, the layered interface having a second surface and the layered interface being adapted for electrically insulating the first surface from the second surface, and a textured surface structure including a plurality of nanowires and a transparent dielectric coating, the textured surface structure being in contact with the second surface of the layered interface, the plurality of nanowires protruding from the second surface and the plurality of nanowires being embedded between the second surface and the transparent dielectric coating.
    Type: Grant
    Filed: December 21, 2015
    Date of Patent: September 1, 2020
    Assignees: TOTAL S.A., ECOLE POLYTECHNIQUE, CENTRE NATIONAL DE LA RECHERCHE SCIENTIFIQUE
    Inventors: Pere Roca I Cabarrocas, Wanghua Chen, Martin Foldyna, Gilles Poulain
  • Publication number: 20180006164
    Abstract: Disclosed is an opto-electronic device including a semiconducting substrate, a layered interface including at least one layer, the layered interface having a first surface in contact with a surface of the semiconducting substrate and the layered interface being adapted for passivating the surface of the semiconducting substrate, the layered interface having a second surface and the layered interface being adapted for electrically insulating the first surface from the second surface, and a textured surface structure including a plurality of nanowires and a transparent dielectric coating, the textured surface structure being in contact with the second surface of the layered interface, the plurality of nanowires protruding from the second surface and the plurality of nanowires being embedded between the second surface and the transparent dielectric coating.
    Type: Application
    Filed: December 21, 2015
    Publication date: January 4, 2018
    Inventors: Pere ROCA I CABARROCAS, Wanghua CHEN, Martin FOLDYNA, Gilles POULAIN