Patents by Inventor Wang N. Chueh

Wang N. Chueh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method of fabricating a read-only memory cell configuration having steep trenches
    Patent number: 5504025
    Abstract: A semiconductor integrated circuit of a read-only memory device having steep trenches is disclosed. The memory device includes a substrate that has a plurality of interwoven chessboard-like trenches, each trench including opposing and sloping side walls. The memory device also includes a plurality of drain/source regions formed on the substrate. Neighboring drain/source regions are positioned, in conformity with the presence of mesas and bottoms of the trenches, in a high and low interwoven manner in a first direction along the plane of the substrate at an altitude relative to the plane of the substrate, thereby forming a generally vertical drain/source channel between each pair of neighboring drain/source regions. The memory device further includes a gate oxide layer formed on the substrate, and a plurality of gate regions formed on the surface of the gate oxide layer.
    Type: Grant
    Filed: November 28, 1994
    Date of Patent: April 2, 1996
    Assignee: United Microelectronics Corp.
    Inventors: Lee Fong-Chun, Fu Chien-Chih, Wang N. Chueh
  • Read-only memory cell configuration with steep trenches
    Patent number: 5453637
    Abstract: A semiconductor integrated circuit of a read-only memory device having steep trenches is disclosed. The memory device includes a substrate that has a plurality of interwoven chessboard-like trenches, each trench including opposing and sloping side walls. The memory device also includes a plurality of drain/source regions formed on the substrate. Neighboring drain/source regions are positioned, in conformity with the presence of mesas and bottoms of the trenches, in a high and low interwoven manner in a first direction along the plane of the substrate at an altitude relative to the plane of the substrate, thereby forming a generally vertical drain/source channel between each pair of neighboring drain/source regions. The memory device further includes a gate oxide layer formed on the substrate, and a plurality of gate regions formed on the surface of the gate oxide layer.
    Type: Grant
    Filed: May 18, 1994
    Date of Patent: September 26, 1995
    Assignee: United Microelectronics Corp.
    Inventors: Lee Fong-Chun, Fu Chien-Chih, Wang N. Chueh